सीपीयू शिल्पों की तुलना

कम्प्यूटर शिल्प (Computer architecture) को प्रायः 8, 16, 32, or 64 बिट आदि के द्वारा समझा जाता है। किन्तु कम्प्यूटर शिल्प में इसके अलावा भी कुछ अन्य डेटा-साइज होते हैं। शिल्प (Architectures) नीचे की सारणी में सीपीयू शिल्प से सम्बन्धित मूलभूत सूचनाओं की ही तुलना की गैइ है। शिल्प बिट संख्या संस्करण कब आया Max # Operands टाइप डिजाइन रजिस्टर इंस्ट्रक्शन इन्कोडिंग ब्रांच इवैलुएशन Endianness Extensions मुक्त रॉयल्टी-मुक्त Alpha 64 1992 3 Register-Register RISC 32 Fixed Condition register Bi Motion Video Instructions MVI, Byte-Word Extensions BWX, Floating-point Extensions FIX, Count Extensions CIX ARM 32 ARMv7 and earlier 1983 3 Register-Register RISC 16 Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit) Condition code Bi NEON, Jazelle, Vector Floating Point VFP, TrustZone, LPAE Large Physical Address Extension ARM 64 ARMv8http://www.arm.com/files/downloads/ARMv8_Architecture.pdf ARMv8 Technology Preview 21 सितंबर 2012 https://web.archive.org/web/20180610181021/https://www.arm.com/files/downloads/ARMv8_Architecture.pdf 10 जून 2018 dead 2011http://www.computerworld.com/s/article/9221262/ARM_goes_64_bit_with_new_ARMv8_chip_architecture/ ARM goes 64-bit with new ARMv8 chip architecture 26 मई 2012 https://web.archive.org/web/20120303171308/http://www.computerworld.com/s/article/9221262/ARM_goes_64_bit_with_new_ARMv8_chip_architecture 3 मार्च 2012 live 3 Register-Register RISC 30 Fixed (32-bit), Thumb: Fixed (16-bit), Thumb-2: Variable (16 and 32-bit), A64 Condition code Bi NEON, Jazelle, Vector Floating Point VFP, TrustZone AVR32 32 Rev 2 2006 2-3 RISC 15 Variablehttp://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf AVR32 Architecture Document Atmel 2008-06-15 https://www.webcitation.org/66FeKiOy0?url=http://www.atmel.com/Images/doc32000.pdf 18 मार्च 2012 dead Big Java Virtual Machine Blackfin 32 2000 RISChttp://www.analog.com/en/embedded-processing-dsp/blackfin/content/blackfin_architecture/fca.html Blackfin Processor Architecture Overview Analog Devices 2009-05-10 https://web.archive.org/web/20090522070045/http://www.analog.com/en/embedded-processing-dsp/blackfin/content/blackfin_architecture/fca.html 22 मई 2009 dead 8 Littlehttp://www.analog.com/FAQs/FAQDisplay.html?DSPKBContentID=752A11D1-9E11-4A7F-91AC-CA3C264C5667 Blackfin memory architecture Analog Devices 2009-12-18 https://web.archive.org/web/20110616182409/http://www.analog.com/FAQs/FAQDisplay.html?DSPKBContentID=752A11D1-9E11-4A7F-91AC-CA3C264C5667 16 जून 2011 dead DLX 32 1990 3 RISC 32 Fixed (32-bit) Big eSi-RISC 16/32 2009 3 Register-Register RISC 8-72 Variable(16 or 32-bit) Compare and branch and condition register Bi User-defined instructions Itanium (IA-64) 64 2001 Register-Register EPIC 128 Condition register Bi (selectable) Intel Virtualization Technology M32R 32 1997 RISC 16 Fixed (16- or 32-bit) Bi m68k 16/32 1979 CISC 16 Big Mico32 32 2006 3 Register-Register RISC 32http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32architecture.cfm LatticeMico32 Architecture Lattice Semiconductor 2009-12-18 https://web.archive.org/web/20100623021729/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32architecture.cfm 23 जून 2010 dead Fixed (32-bit) Compare and branch Big User-defined instructions http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32opensourcelicensing.cfm Open Source Licensing Lattice Semiconductor 2009-12-18 https://web.archive.org/web/20100620185845/http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/mico32opensourcelicensing.cfm 20 जून 2010 dead MIPS 64 (32→64) 5 1981 3 Register-Register RISC 32 Fixed (32-bit) Condition register Bi MDMX, MIPS-3D MMIX 64 1999 3 Register-Register RISC 256 Fixed (32-bit) Big PA-RISC (HP/PA) 64 (32→64) 2.0 1986 3 RISC 32 Fixed Compare and branch Big Multimedia Acceleration eXtensions (MAX), MAX-2 PowerPC 32/64 (32→64) 2.06http://www.power.org/resources/downloads/PowerISA_V2.06_PUBLIC.pdf Power ISA V2.06 IBM 2009-07-04 6 दिसंबर 2022 https://web.archive.org/web/20221206035952/http://www.power.org/resources/downloads/PowerISA_V2.06_PUBLIC.pdf dead 1991 3 Register-Register RISC 32 Fixed, Variable Condition code Big/Bi AltiVec, APU, VSX, Cell http://www.ibm.com/developerworks/power/newto/#2 https://web.archive.org/web/20120829033421/http://www.ibm.com/developerworks/power/newto/#2 29 अगस्त 2012 New to Cell/B.E., multicore, and Power Architecture technology S+core 16/32 2005 RISC Little Series 32000 32 1982 5 Memory-Memory CISC 8 Variable Huffman coded, up to 23 bytes long Condition Code Little BitBlt instructions SPARC 64 (32→64) V9 1985 3 Register-Register RISC 31 (of at least 55) Fixed Condition code Big → Bi VIS 1.0, 2.0, 3.0 http://www.sparc.org/specificationsDocuments.html# https://web.archive.org/web/20120222225719/http://www.sparc.org/specificationsDocuments.html 22 फ़रवरी 2012 #ArchLic SPARC Architecture License SuperH (SH) 32 1990s 2 Register-Register/ Register-Memory RISC 16 Fixed Condition Code (Single Bit) Bi System/360 / System/370 / z/Architecture 64 (32→64) 3 1964 Register-Memory/Memory-Memory CISC 16 Fixed Condition code Big VAX 32 1977 6 Memory-Memory CISC 16 Variable Compare and branch Little VAX Vector Architecture x86 32 (16→32) 1978 2 Register-Memory CISC 8 Variable Condition code Little MMX, 3DNow!, SSE, PAE, x86-64 64 2003 2 Register-Memory CISC 16 Variable Condition code Little MMX, 3DNow!, PAE, AVX सूक्ष्मशिल्प (Microarchitectures) नीचे की सारणी में प्रमुख सूक्ष्मशिल्पों की तुलना की गई है। Microarchitecture Pipeline stages Misc AMD K5 Out-of-order execution, register renaming, speculative execution AMD K6 Superscalar, branch prediction AMD K6-III Branch prediction, speculative execution, out-of-order executionhttp://www.amd.com/us-en/Processors/ProductInformation/0, 30_118_1260_1288%5E1295,00.html AMD K7 Out-of-order execution, branch prediction, Harvard architecture AMD K8 64-bit, integrated memory controller, 16 byte instruction prefetching AMD K10 Superscalar, out-of-order execution, 32-way set associative L3 victim cache, 32-byte instruction prefetching ARM7TDMI(-S) 3 ARM7EJ-S 5 ARM810 5 ARM9TDMI 5 ARM1020E 6 XScale PXA210/PXA250 7 ARM1136J(F)-S 8 ARM1156T2(F)-S 9 ARM Cortex-A5 8 ARM Cortex-A8 13 ARM Cortex-A9 Out-of-order, speculative issue, superscalar ARM Cortex-A15 Multicore (up to 16) AVR32 AP7 7 AVR32 UC3 3 Harvard architecture Bobcat Out-of-order execution Bulldozer Shared L3 cache, multithreading, multicore, integrated memory controller Crusoe In-order execution, 128-bit VLIW, integrated memory controller Efficeon In-order execution, 256-bit VLIW, fully integrated memory controller Cyrix Cx5x86 6http://www.pcguide.com/ref/cpu/fam/g4C5x86-c.html संग्रहीत प्रति 21 सितंबर 2012 https://web.archive.org/web/20120504235323/http://pcguide.com/ref/cpu/fam/g4C5x86-c.html 4 मई 2012 dead Branch prediction Cyrix 6x86 Superscalar, superpipelined, register renaming, speculative execution, out-of-order execution DLX 5 eSi-3200 5 In-order, speculative issue eSi-3250 5 In-order, speculative issue EV4 (Alpha 21064) Superscalar EV7 (Alpha 21364) Superscalar design with out-of-order execution, branch prediction, 4-way SMT, integrated memory controller EV8 (Alpha 21464) Superscalar design with out-of-order execution P5 (Pentium) 5 Superscalar P6 (Pentium Pro) 14 Speculative execution, Register renaming, superscalar design with out-of-order execution P6 (Pentium II) Branch prediction P6 (Pentium III) 10 Itanium 8Intel Itanium 2 Processor Hardware Developer's Manual. p. 14. <http://www.intel.com/design/itanium2/manuals/25110901.pdf https://web.archive.org/web/20061212164540/http://www.intel.com/design/itanium2/manuals/25110901.pdf 12 दिसंबर 2006 > (2002) [Retrieved November 28, 2011] Speculative execution, branch prediction, register renaming, 30 execution units, multithreading NetBurst (Willamette) 20 Simultaneous multithreading NetBurst (Northwood) 20 Simultaneous multithreading NetBurst (Prescott) 31 Simultaneous multithreading NetBurst (Cedar Mill) 31 Simultaneous multithreading Core 14 Intel Atom 16 Simultaneous multithreading, in-order. No instruction reordering, speculative execution, or register renaming. Nehalem Simultaneous multithreading, integrated memory controller, L1/L2/L3 cache Sandy Bridge Simultaneous multithreading, multicore, integrated memory controller, L1/L2/L3 cache. 2 threads per core. Haswell 14 Multicore LatticeMico32 6 Harvard architecture POWER1 Superscalar, out-of-order execution POWER3 Superscalar, out-of-order execution POWER4 Superscalar, speculative execution, out-of-order execution POWER5 Simultaneous multithreading, out-of-order execution, integrated memory controller POWER6 2-way simultaneous multithreading, in-order execution POWER7 4 SMT threads per core, 12 execution units per core PowerPC 401 3 PowerPC 405 5 PowerPC 440 7 PowerPC 470 9 SMP PowerPC A2 15 PowerPC e300 4 Superscalar, Branch prediction PowerPC e500 Dual 7 stage Multicore PowerPC e600 3-issue 7 stage Superscalar out-of-order execution, branch prediction PowerPC e5500 4-issue 7 stage Out-of-order, multicore PowerPC 603 4 5 execution units, branch prediction. No SMP. PowerPC 603q 5 In-order PowerPC 604 6 Superscalar, out-of-order execution, 6 execution units. SMP support. PowerPC 620 5 Out-of-order execution- SMP support. PWRficient Superscalar, out-of-order execution, 6 execution units R4000 8 Scalar StrongARM SA-110 5 Scalar, in-order SuperH SH2 5 SuperH SH2A 5 Superscalar, Harvard architecture SPARC Superscalar HyperSPARC Superscalar SuperSPARC Superscalar, in-order SPARC64 VI/VII/VII+ Superscalar, out-of-orderhttp://www.fujitsu.com/global/services/computing/server/sparcenterprise/technology/performance/processor.html संग्रहीत प्रति 21 सितंबर 2012 https://web.archive.org/web/20120922084952/http://www.fujitsu.com/global/services/computing/server/sparcenterprise/technology/performance/processor.html 22 सितंबर 2012 dead UltraSPARC 9 UltraSPARC T1 6 Open source, multithreading, multi-core, 4 threads per core, integrated memory controller UltraSPARC T2 8 Open source, multithreading, multi-core, 8 threads per core SPARC T3 8 Multithreading, multi-core, 8 threads per core, SMP SPARC T4 16 Multithreading, multi-core, 8 threads per core, SMP, out-of-order VIA C7 In-order execution VIA Nano (Isaiah) Superscalar out-of-order execution, branch prediction, 7 execution units WinChip 4 In-order execution इन्हें भी देखें सीपीयू (CPU) इन्स्ट्रक्शन सेट माइक्रोप्रोसेसर सन्दर्भ श्रेणी:कम्प्यूटर शिल्प