411 REFERENCE · Wikipedia
इंटेल चिपसेटों की सूची
Reference material by Wikipedia contributors. This retains its source identity and is not 411 news reporting.
thumb|300px|पेंटियम डुअल-कोर माइक्रोप्रोसेसर के साथ इंटेल i945GC नॉर्थब्रिज
यह लेख इंटेल द्वारा निर्मित मदरबोर्ड चिपसेट की एक सूची प्रदान करता है, जिन्हें तीन मुख्य श्रेणियों में विभाजित किया गया है: वे जो इंटरकनेक्शन (4xx श्रृंखला) के लिए पीसीआई बस का उपयोग करते हैं, वे जो विशेष "हब लिंक्स" (8xx श्रृंखला) का उपयोग करके कनेक्ट होते हैं, और वे जो PCI एक्सप्रेस (9xx सीरीज़) का उपयोग करके कनेक्ट होते हैं। चिपसेट को कालानुक्रमिक क्रम में सूचीबद्ध किया गया है।
चिपसेट के आने से पहले की स्थिति
प्रारंभिक IBM XT संगत मदरबोर्ड में चिपसेट नहीं था, बल्कि वे इंटेल द्वारा निर्मित TTL संग्रह पर निर्भर होते थे:।PC Based Instrumentation and Control https://archive.org/details/pcbasedinstrumen00bami_789 Michael H. Tooley 32 Elsevier 2005 9780750647168
the 8284 clock generator
the 8288 bus controller
the 8254 Programmable Interval Timer
the 8255 parallel I/O interface
the 8259 Programmable Interrupt Controller
the 8237 DMA controller
प्रारंभिक चिपसेट
ICयो की एक छोटी सन्ख्या में एक मेनबोर्ड पर होने वाले आवश्यक कार्यों को एकीकृत करने के लिए, इंटेल ने अपने इंटेल 80286 और इंटेल 80386SX प्रोसेसर के लिए ZYMOS POACH चिपसेट को लाइसेंस दिया (the 82230/82231 High Integration AT-Compatible Chip Set). इंटेल 386SX को समर्थन(support) प्रदान करने के लिए इस चिपसेट का उपयोग एक 82335 हाई-इंटीग्रेशन इंटरफेस डिवाइस के साथ किया जा सकता है।
प्रारंभिक इंटेल चिपसेट की सूची में शामिल हैं:ftp://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf Archived copy 2008-09-02 dead https://web.archive.org/web/20080910041059/http://download.intel.com/museum/research/arc_collect/timeline/TimelineDateSort7_05.pdf 2008-09-10 Time Line 1980-1989
http://www.intel-vintage.com/timeline19801989.htm
2012-01-14
https://web.archive.org/web/20120113013236/http://www.intel-vintage.com/timeline19801989.htm
13 जनवरी 2012
dead
82091AA EISA/ISA - Advanced Integrated Peripheral (AIP), includes: floppy disk controller, 2× UARTs, parallel port, IDE controller, oscillator, etc.82091AA ADVANCED INTEGRATED PERIPHERAL (AIP) http://www.intel.com/design/archives/periphrl/docs/29048603.htm 2013-08-02 https://web.archive.org/web/20140116221203/http://www.intel.com/design/archives/periphrl/docs/29048603.htm 2014-01-16 live
82310 MCA - announced in April 1988. PS/2 Model 80 Clones Based on Intel Chipset
Tom
Moran
InfoWorld
April 25, 1988
1
https://books.google.com/books?id=pj0EAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627025936/http://books.google.com/books?id=pj0EAAAAMBAJ
June 27, 2014
live
Includes: 82306 Local Channel Support Chip, 82307 DMA Controller/Central Arbiter, 82308 Micro Channel Bus Controller, 82309 Address Bus Controller, 82706 VGA Graphics Controller.https://archive.org/details/bitsavers_inteldataBrocessorandPeripheralHandbookVol1_114989017 1989 Intel Microprocessor and Peripheral Handbook Vol 1 Internet Archive 2016-08-18 https://web.archive.org/web/20160703235950/https://archive.org/details/bitsavers_inteldataBrocessorandPeripheralHandbookVol1_114989017 2016-07-03 live
82350 EISA - announced in September 1988. New EISA Features Set It Apart From the AT Bus
Tom
Moran
Ed
Scannel
InfoWorld
September 26, 1988
23
https://books.google.com/books?id=kDoEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627025440/http://books.google.com/books?id=kDoEAAAAMBAJ
June 27, 2014
live
82311 MCA - announced in November 1988. MCA Multiprocessing In the Works at Intel
Martin
Marshall
InfoWorld
November 14, 1988
1
https://books.google.com/books?id=wTsEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20170227013930/https://books.google.com/books?id=wTsEAAAAMBAJ
February 27, 2017
live
Intel Introduces the Second Generation Micro Channel Chip Set
November 29, 1988 Includes: 82303 and 82304 Local I/O Channel Support Chips, 82307 DMA Controller/Central Arbiter, 82308 Micro Channel Bus Controller, 82309 Address Bus Controller, 82706 VGA Graphics Controller, 82077 Floppy Disk Controller. Uncorking the future
Mark
Brownstein
InfoWorld
November 13, 1989
101
https://books.google.com/books?id=sTAEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627030045/http://books.google.com/books?id=sTAEAAAAMBAJ
June 27, 2014
live
82320 MCA - announced in April 1989. Intel Adds Low-Power 386SX To List of Chip Announcements
Ron
Copeland
InfoWorld
April 17, 1989
105
https://books.google.com/books?id=CDoEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627030632/http://books.google.com/books?id=CDoEAAAAMBAJ
June 27, 2014
live
82340SX PC AT - announced in January 1990, it is the Topcat chipset licensed from VLSI. Intel to Market VLSI Topcat Chips
Ron
Copeland
InfoWorld
January 8, 1990
3
https://books.google.com/books?id=dzAEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627030754/http://books.google.com/books?id=dzAEAAAAMBAJ
June 27, 2014
live
82340DX PC AT - announced in January 1990, it is the Topcat chipset licensed from VLSI.
82360SL - announced in October 1990. Intel to Introduce 20-MHz Chip Set
Nico
Krohn
InfoWorld
October 15, 1990
5
https://books.google.com/books?id=LjwEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627024041/http://books.google.com/books?id=LjwEAAAAMBAJ
June 27, 2014
live
It was a chipset for the mobile 80386SL and 80486SL processors. It integrated DMA controller, an interrupt controller PIC, serial and parallel ports, and power-management logic for the processor.
82350DT EISA - announced in April 1991. Intel Debuts EISA Chip Set for Lower Cost 32-Bit Systems
Louise
Fickel
InfoWorld
April 29, 1991
28
https://books.google.com/books?id=y1AEAAAAMBAJ
October 15, 2016
https://web.archive.org/web/20140627025609/http://books.google.com/books?id=y1AEAAAAMBAJ
June 27, 2014
live
4xx chipsets
80486 chipsets
Chipset Code Name Part Numbers South Bridge Release Date Processors FSB SMP Memory types Max. memory Parity/ECC L2 Cache Type PCI support420TX Saturn 82424TX, 82423TX SIO November 1992 5 V 486 Up to 33 MHz rowspan="3" FPM 128 MBWhen applied to computer memory (RAM or cache) the quantities KB, MB and GB are defined as:
1 KB = 1024 B,
1 MB = 1024 KB,
1 GB = 1024 MB,
consistent with the JEDEC memory standard. rowspan="3" Parity Async. 1.0420ZX Saturn II 82424ZX, 82423TX March 1994 5 V/3.3 V 486 160 MB 2.1420EX Aries 82425EX 82426EX Up to 50 MHz 128 MB 2.0
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