Digital Electronics/Logic Gates/Logic NAND

Logic NAND NAND gates are one of the two basic logic gates (the other being NOR logic) from which any other logic gates can be built. Due to this property, NAND and NOR gates are sometimes called "universal gates". However, modern integrated circuits are not constructed exclusively from a single type of gate. Instead, EDA tools are used to convert the description of a logical circuit to a netlist of complex gates (standard cells) or transistors (full custo] approach). NOT A NOT gate is made by joining the inputs of a NAND gate. Since a NAND gate is equivalent to an AND gate followed by a NOT gate, joining the inputs of a NAND gate leaves only the NOT part. Desired GateNAND ConstructionImage:NOT ANSI Labelled.svgImage:NOT from NAND.svg+Truth Table Input A Output Q 0 1 1 0 AND An AND gate is made by following a NAND gate with a NOT gate as shown below. This gives a NOT NAND, i.e. AND. Desired GateNAND ConstructionImage:AND ANSI Labelled.svgImage:AND from NAND.svg+Truth Table Input A Input B Output Q 0 0 0 0 1 0 1 0 0 1 1 1 OR If the truth table for a NAND gate is examined or by applying De Morgan's Laws, it can be seen that if any of the inputs are 0, then the output will be 1. However to be an OR gate, if any input is 1, the output must also be 1. Therefore, if the inputs are inverted, any high input will trigger a high output. Desired GateNAND ConstructionImage:OR ANSI Labelled.svgImage:OR from NAND.svg+Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 1 NOR A NOR gate is simply an OR gate with an inverted output: Desired GateNAND ConstructionImage:NOR ANSI Labelled.svgImage:NOR from NAND.svg+Truth Table Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 0 XOR An XOR gate is made by connecting four NAND gates as shown below. This effectively represents the formula: "(A NAND (A NAND B)) NAND (B NAND (A NAND B))". Desired GateNAND ConstructionImage:XOR ANSI Labelled.svgImage:XOR from NAND.svg+Truth Table Input A Input B Output Q 0 0 0 0 1 1 1 0 1 1 1 0 XNOR An XNOR gate is simply an XOR gate with an inverted output: Desired GateNAND ConstructionImage:XNOR ANSI Labelled.svgImage:XNOR from NAND.svg+Truth Table Input A Input B Output Q 0 0 1 0 1 0 1 0 0 1 1 1