Super NES Programming/Super FX tutorial

Introduction The Super FX is a custom 16-bit RISC processor with a special bitmap emulation function designed for the SNES. It was designed to bring rudimentary 3D capabilities to the SNES. Programming for it is done with special Super FX assembly language. Each Super FX title uses a combination of standard SNES assembly code with specially compiled Super FX assembly routines coded as binary data in the cartridge. It can run in parallel with the SNES under certain conditions. Each Super FX cartridge has on-board RAM which the Super FX chip uses as a frame buffer and for general purpose operations which it can share with the SNES. Existing Titles The Super FX chip was used in 8 released SNES games, in Star Fox 2 (unreleased) and in multiple tech demos; 2 of which binaries are available. Title Super FX Version ROM Size Game Pak RAM Size Save RAM Size Star Fox (PAL: Starwing) Mario Chip 8 MBit 256 KBit None Dirt Racer GSU-1 4 MBit 256 KBit None Dirt Trax FX GSU-1 4 MBit 512 KBit None Stunt Race FX (JP: Wild Trax) GSU-1 8 MBit 512 KBit 64KBit Star Fox 2 GSU-1 8 MBit 512 KBit 64KBit Vortex GSU-1 4 MBit 256 KBit None SNES Voxel Landscape Demo GSU-1 3 MBit 512 KBit None Powerslide (demo) GSU-1 3 MBit 512 KBit None DOOM GSU-2 16 MBit 512 KBit None Yoshi's Island GSU-2-SP1 16 MBit 256 KBit 64KBit Winter Gold GSU-2 16 MBit 512 KBit 64KBit Theory of Operation thumb|A Super FX co-processor. The Super FX is a co-processor for the SNES CPU. The Super FX's task is to execute complex mathematical calculations much faster than the SNES and to generate bitmap pictures for simple 3D rendering of Super FX games. The Super FX and SNES processors share access to a common Game Pak RAM and ROM bus. Only one processor, the Super FX or SNES CPU, may access the Game Pak RAM and/or ROM at any time, controlled by special registers. The flow of the SNES and Super FX accessing the data busses is an art in optimizing the program's efficiency. The Game Pak RAM is mainly used for storing results of calculations, a Super FX program, bulk data, or a PLOT picture the Super FX is generating. There can be 256 Kib (32KiB) or 512 Kib (64 KiB) of RAM. Some Super FX games have also used this RAM to store save data. The Super FX can process instructions in 3 ways: reading them from Game Pak RAM, from the Game Pak ROM (reading straight out of the ROM chip), or via a special 512 byte instruction cache. It is possible for the Super FX to run in parallel with the SNES CPU when using the 512 byte instruction Cache. It involves loading a program in, and then setting the Super FX to start its work. The 512 byte cache is in general 3x faster compared to running the program in the Game Pak RAM or ROM. The Super FX can interrupt the SNES CPU after it finishes processing. When using the Super FX's special bitmap functions, it's possible to quickly load the bitmap out of Game Pak RAM into the SNES Video RAM and display it on the screen. The SNES by default is a tile and sprite based console - pixel based scene construction used in 3D rendered games is very inefficient with stock SNES hardware. In Super FX games such as DOOM, Star Fox/Starwing and the like, the Super FX is rapidly painting pixel based scene bitmaps onto the Game Pak RAM and then throwing it into the SNES VRAM for graphics display many times per second. Hardware Revisions There are 3 different hardware revisions of the Super FX. All revisions are functionally compatible in terms of instruction set but support different ROM sizes. MARIO Chip - which stands for Mathematical Argonaut Rotation Input Output. The first release of the Super FX chip and was only used with Star Fox/Starwing. There are two versions of the chip - one with a direct PCB die bonded/epoxied setup and one with a standard chip carrier package. GSU-1 - the release used on most Super FX games in a standard chip carrier package. Functionally identical to MARIO Chip. Supports a maximum 8 Megabit (1 Megabyte) ROM size. GSU-2 - used on the final 3 Super FX games, supports the full 16 Megabit (2 Megabyte) ROM size. Registers The Super FX chip has 16 general-purpose 16-bit registers labeled R0 to R15 plus 11 control registers. Additionally, a memory space from $3100-$32FF forms the instruction cache. General-Purpose Registers RegisterAddressDescriptionAccess from SNESR0$3000 default source/destination register R/WR1$3002 pixel plot X position register R/WR2$3004 pixel plot Y position register R/WR3$3006 for general use R/WR4$3008 lower 16 bit result of lmult R/WR5$300A for general use R/WR6$300C multiplier for fmult and lmult R/WR7$300E fixed point texel X position for merge R/WR8$3010 fixed point texel Y position for merge R/WR9$3012 for general use R/WR10$3014 for general use R/WR11$3016 return address set by link R/WR12$3018 loop counter R/WR13$301A loop point address R/WR14$301C rom address for GETB, GETBH, GETBL, GETBSR/WR15$301E program counter R/W Control Registers NameAddressDescriptionSizeAccess from SNESSFR $3030 status flag register 16 bits R/W $3032 unused BRAMR $3033 Backup RAM register 8 bitsWPBR $3034 program bank register 8 bits R/W $3035 unused ROMBR $3036 rom bank register 8 bits RCFGR $3037 control flags register 8 bitsWSCBR $3038 screen base register 8 bitsWCLSR $3039 clock speed register 8 bitsWSCMR $303A screen mode register 8 bitsWVCR $303B version code register (read only) 8 bits RRAMBR $303C RAM bank register 8 bitsR $303D unused CBR $303E cache base register 16 bitsR Instruction Cache NameAddressDescriptionSizeAccess from SNES1 $3100 First byte of instruction cache 8 bits R/W2 $3101 Second byte of instruction cache 8 bitsR/W ... ... ... 8 bitsR/W ... ... ... 8 bitsR/W512 $32FF Five hundred and twelfth byte of instruction cache 8 bitsR/W SFR Status Flag Register The SFR is a very important register. It controls branching within the Super FX after evaluating a calculation and can determine the status of the Super FX when accessed from the SNES CPU. Bit Description 0 - 1 Z Zero flag 2 CY Carry flag 3 S Sign flag 4 OV Overflow flag 5 G Go flag (set to 1 when the GSU is running) 6 R Set to 1 when reading ROM using R14 address 7 - 8 ALT1 Mode set-up flag for the next instruction 9 ALT2 Mode set-up flag for the next instruction10 IL Immediate lower 8-bit flag11 IH Immediate higher 8-bit flag12 B Set to 1 when the WITH instruction is executed13 -14 -15 IRQ Set to 1 when GSU caused an interrupt. Set to 0 when read by 65c816 BRAMBR Backup RAM Register Used to allow protection of the Back-up RAM (not to be confused with Game Pak RAM) inside the Game Pak. Bit 0 can be set to 0 to disable writing to Back-up RAM, and 1 to enable writing. Bit Description 0 BRAM Flag (0 = write disable, 1=write enable) 1 Not Used 2 Not Used 3 Not Used 4 Not Used 5 Not Used 6 Not Used 7 Not Used PBR Program Bank Register When the Super FX is loading code it references the PBR register to specify the bank being used. The LJMP instruction is the general method used to change this register. Bit Description 0 A16 Address Select 1 A17 Address Select 2 A18 Address Select 3 A19 Address Select 4 A20 Address Select 5 A21 Address Select 6 A22 Address Select 7 A23 Address Select ROMBR Game Pak ROM Bank Register When using the ROM buffering system, this register specifies the bank of the Game Pak ROM being copied into the buffer. The ROMB instruction is the general method used to change this register. Bit Description 0 A16 ROM Address Select 1 A17 ROM Address Select 2 A18 ROM Address Select 3 A19 ROM Address Select 4 A20 ROM Address Select 5 A21 ROM Address Select 6 A22 ROM Address Select 7 A23 ROM Address Select CFGR Config Register Controls the clock multiplier and interrupt mask. Bit Description 0 Not used 1 Not Used 2 Not Used 3 Not Used 4 Not Used 5 MS0 (0=standard,1=high speed) 6 Not Used 7 IRQ (0=normal, 1=masked) Note: If set to run at 21.477 MHz through the CLSR flag(1), MS0 flag should be set to 0. SCBR Screen Base Register This register sets the starting address of the graphics storage area. It is written to directly, rather than through a specific instruction. Bit Description 0 A10 Screen Base Select 1 A11 Screen Base Select 2 A12 Screen Base Select 3 A13 Screen Base Select 4 A14 Screen Base Select 5 A15 Screen Base Select 6 A16 Screen Base Select 7 A17 Screen Base Select CLSR Clock Register Controls the clock frequency of the Super FX chip. Bit Description 0 CLSR, 0=10.738 MHz, 1=21.477 MHz 1 Not Used 2 Not Used 3 Not Used 4 Not Used 5 Not used 6 Not Used 7 Not used SCMR Screen Mode Register This register sets the number of colors and screen height for the PLOT graphics acceleration routine and additionally controls whether the Super FX or SNES has control of the Game Pak RAM and ROM. Bit Description 0 Color Mode MD0 1 Color Mode MD1 2 Screen Height HT0 3 Game Pak RAM Access - RAN (0=SNES,1=Super FX) 4 Game Pak ROM Access - RON (0=SNES,1=Super FX) 5 Screen Height HT1 6 Not used 7 Not used Screen Height Truth Table HT1 HT0 Mode 0 0 128 pixels 0 1 160 pixels 1 0 192 pixels 1 1 OBJ Mode Color Mode Truth Table MD1 MD0 Mode 0 0 4 colors 0 1 16 colors 1 0 Not used 1 1 256 colors VCR Version Register Can read out the version of the Super FX chip in use with this register Bit Description 0 VC0 1 VC1 2 VC2 3 VC3 4 VC4 5 VC5 6 VC6 7 VC7 RAMBR Game Pak RAM Bank Register When writing between the Game Pak RAM and the Super FX registers, this register specifies the bank of the Game Pak RAM being used. The RAMB instruction is the general method used to change this register. Bit 0 is used to set the RAM bank to $70 or $71 Bit Description 0 A16 ($70 when 0, $71 when 1) 1 Not Used 2 Not Used 3 Not Used 4 Not Used 5 Not Used 6 Not Used 7 Not Used CBR Cache Base Register This register specifies the address of either the Game Pak RAM or ROM where data will be loaded from into the cache. Both the LJMP and CACHE instructions are accepted ways to change this register. Bit Description 0 - (0 when read always) 1 - (0 when read always) 2 - (0 when read always) 3 - (0 when read always) 4 A4 5 A5 6 A6 7 A7 8 A8 9 A910 A1011 A1112 A1213 A1314 A1415 A15 Memory Map From SNES CPU Point of View Super FX Interface: Mapped to $3000-$32FF, in banks $00-$3F and $80-$BF Game ROM: Mapped to 2MiB in banks $00-$3F from $8000-$FFFF. 2MiB mirror mapped from banks $40-$5F. Game Pak RAM: Mapped to 128KiB starting from bank $70:$0000. First 8KiB mirrored to $6000 in each of banks $00-$3F and $80-$BF. Game Back-up RAM: Mapped to 128KiB from bank $78:$0000 SNES CPU ROM: An additional 6MiB ROM only accessible to the SNES CPU could be used, but no Super FX games went above 2MiB. The additional ROM would've been mapped in banks $80-$BF from $8000-$FFFF and in banks $C0-$FF from $0000-$FFFF From Super FX Point of View Game ROM: Mapped to 2MiB in banks $00-$3F from $8000-$FFFF. 2MiB mirror mapped from banks $40-$5F. Game Pak RAM: Mapped to 128KiB starting from Bank $70:$0000. Other memory locations viewable from the SNES should not be addressed. Note: The Super FX accesses memory through three bank control registers: Program Bank Register(PBR), ROM Bank Register (ROMBR) and RAM Bank Register (RAMBR) Instruction Set Super FX The Super FX instruction set is different from the Super Nintendo's native instruction set. It allows faster, more sophisticated 16-bit mathematical functions and includes some specific graphics manipulation functions. Some instructions can be assembled as a single byte. This is where both the instruction(nibble) and argument(nibble) are co-joined into the same storage byte. This allows for faster execution and also greater instruction density. These are important objectives when designing a co-processor. One such instruction is ADC, which starts as $5 and takes an argument of one of the 16 general purpose Super FX registers($0-$F). Quite a few instructions require an ALT instruction to be executed before the opcode. This modifies the behavior of the same opcode to perform a slightly different operation. There are 3 possible ALT codes - ALT1($3D), ALT2($3E), and ALT1+ALT2($3F). In the table below, the specific ALT code is listed for each instruction. Most instructions rely on pre-defined pointers for the locations of calculation variables. These are the FROM, TO and WITH instructions. The TO and FROM commands specify the general purpose register that is the variable, and the calculation result respectively. WITH defines both of the variable/result in the same command. The variable and result are known as the source and destination registers respectfully. Instruction Set Table InstructionDescriptionALT(Hex)CODE(HEX)ARGLength(B)BATL1ALT2O/VSCYZROMRAMCacheClassificationNoteADCAdd with carry3D0x5Rn2000****662Arithmetic Operation InstructionsADCAdd with carry3F0x5#n2000****662Arithmetic Operation InstructionsADDAddNone0x5Rn1000****331Arithmetic Operation InstructionsADDAdd3E0x5#n2000****662Arithmetic Operation InstructionsALT1Set ALT1 modeNone0x3D/1/1/////331Prefix Flag InstructionsALT2Set ALT2 modeNone0x3E/1//1////331Prefix Flag InstructionsALT3Set ALT3 modeNone0x3F/1/11////331Prefix Flag InstructionsANDLogical ANDNone0x7Rn1000/*/*331Logical Operation InstructionsANDLogical AND3E0x7#n2000/*/*662Logical Operation InstructionsASRArithmetric Shift RightNone0x96/1000/***331Shift InstructionsBCCBranch on carry clearNone0x0Ce2///////662"Jump, Branch and Loop Instructions"BCSBranch on carry setNone0x0De2///////662"Jump, Branch and Loop Instructions"BEQBranch on equalNone0x09e2///////662"Jump, Branch and Loop Instructions"BGEBranch on greater than or equal to zeroNone0x06e2///////662"Jump, Branch and Loop Instructions"BICBit clear mask3D0x7Rn2000/*/*662Logical Operation InstructionsBICBit clear mask3F0x7#n2000/*/*662Logical Operation InstructionsBLTBranch on less than zeroNone0x07e2///////662"Jump, Branch and Loop Instructions"BMIBranch on minusNone0x0Be2///////662"Jump, Branch and Loop Instructions"BNEBranch on not equalNone0x08e2///////662"Jump, Branch and Loop Instructions"BPLBranch on plusNone0x0Ae2///////662"Jump, Branch and Loop Instructions"BRABranch alwaysNone0x05e2///////662"Jump, Branch and Loop Instructions"BVCBranch on overflow clearNone0x0Ee2///////662"Jump, Branch and Loop Instructions"BVSBranch on overflow setNone0x0Fe2///////662"Jump, Branch and Loop Instructions"CACHESet cache base registerNone0x02/1000////3-43-41GSU Control InstructionsCMODESet Plot mode3D0x4E/2000////662Plot/related instructionsCMPCompare3F0x6Rn2000****662Arithmetic Operation InstructionsCOLORSet plot colorNone0x4E/1000////331Plot/related instructionsDECDecrementNone0xERn1000/*/*331Arithmetic Operation InstructionsDIV2Divide by 23D0x96/2000/***662Arithmetic Operation InstructionsFMULTFractional signed multiplyNone0x9F/1000/***11 or 711 or 78 or 4Arithmetic Operation InstructionsCycles Depends onCFGR RegisterFROMSet SregNone0xBRn1///////331Prefix Register InstructionsGETBGet byte from ROM bufferNone0xEF/1000////3-83-81-6Data Transfer From Game Pak ROM to registerCycles varies due to ROM bufferGETBHGet high byte from ROM buffer3D0xEF/2000////6-106-92-6Data Transfer From Game Pak ROM to registerCycles varies due to ROM bufferGETBLGet low byte from ROM buffer3E0xEF/2000////6-106-92-6Data Transfer From Game Pak ROM to registerCycles varies due to ROM bufferGETBSGet signed byte from ROM buffer3F0xEF/2000////6-106-92-6Data Transfer From Game Pak ROM to registerCycles varies due to ROM bufferGETCGet byte from ROM to color registerNone0xDF/1000////3-103-91-6Data Transfer From Game Pak ROM to registerCycles varies due to ROM bufferHIBValue of high byte of registerNone0xC0/1000/*/*331Byte transfer InstructionsIBTLoad immediate byte dataNone0xA"Rn, #pp"2000////662Data Transfer / Immediate data to registerINCIncrementNone0xDRn1000/*/*331Arithmetic Operation InstructionsIWTLoad immediate word dataNone0xF"Rn, #xx"3000////993Data Transfer / Immediate data to registerJMPJumpNone0x9Rn1000////331"Jump, Branch and Loop Instructions"LDBLoad byte data from RAM3D0x4Rm1000////11136Data Transfer From Game Pak RAM to registerLDWLoad word data from RAMNone0x4Rm1000////10127Data Transfer From Game Pak RAM to registerLEALoad effective addressNone0xF"Rn, xx"3000////993Macro InstructionsLINKLink Return AddressNone0x9#n1000////331"Jump, Branch and Loop Instructions"LJMPLong jump3D0x9Rn2000////662"Jump, Branch and Loop Instructions"LM"Load word data from RAM, using 16 bits"3D0xF"Rn, (xx)"2000////202111Data Transfer From Game Pak RAM to registerLMS"Load word data from RAM, short address"3D0xA"Rn, (yy)"2000////171710Data Transfer From Game Pak RAM to registerLMULT16x16 signed multiply3D0x9F/2000/***10 or 1410 or 145 or 9Arithmetic Operation InstructionsCycles Depends on CFGR RegisterLOBValue of low byte of registerNone0x9E/1000/*/*331Byte transfer InstructionsLOOPLoopNone0x3C/1000/*/*331"Jump, Branch and Loop Instructions"LSRLogical shift rightNone0x03/1000/0**331Shift InstructionsMERGEMerge high byte of R8 and R7None0x70/1000////662Byte transfer InstructionsMOVEMove word data from Rn' to RnNone0x2n1n'"Rn, Rn'"2000////662Data transfer register to registerMOVESMove word data from Rn' to Rn and set flagsNone0x2nBn'"Rn, Rn'"2000////662Data transfer register to registerMULTSigned multiplyNone0x8Rn1000/*/*3 or 53 or 51 or 2Arithmetic Operation InstructionsCycles Depends on CFGR RegisterMULTSigned multiply3E0x8#n2000/*/*6 or 86 or 82 or 3Arithmetic Operation InstructionsCycles Depends on CFGR RegisterNOPNo operationNone0x01/1000////331GSU Control InstructionsNOTInvert all bitsNone0x4F/1000////331Bitwise Operation InstructionsORBitwise ORNone0xCRn1000////331Bitwise Operation InstructionsORBitwise OR3E0xC#n2000////662Bitwise Operation InstructionsPLOTPlot pixelNone0x4C/1000////3-483-511-48Plot/related instructionsCycles varies due to RAM buffer and programRAMBSet RAM data bank3E0xDF/2000////662Bank Set/up InstructionsROLRotate left through carryNone0x04/1000/***331Shift InstructionsROMBSet ROM Data bank3F0xDF/2000////662Bank Set/up InstructionsRORRotate right through carryNone0x97/1000/***331Shift InstructionsRPIXRead pixel color3D0x4C/2000/*/*24-8024-7820-74Plot/related instructionsSBCSubtract with carry3D0x6Rn2000****662Arithmetic Operation InstructionsSBK"Store word data, last RAM address used"None0x9/1000////3-87-111-6Data Transfer From register to Game Pak RAMSEXSign extend registerNone0x95/1000/*/*331Byte transfer InstructionsSMStore word data to RAM using 16 bits3E0xF"Rn, (xx)"3000////12-1716-204-9Data Transfer From register to Game Pak RAMCycles varies due to RAM buffer and programSMS"Store word data to RAM, short address"3E0xA"Rn, (yy)"3000////9-1413-173-8Data Transfer From register to Game Pak RAMCycles varies due to RAM buffer and programSTBStore byte data to RAM3D0x3Rm2000////6-98-142-5Data Transfer From register to Game Pak RAMCycles varies due to RAM buffer and programSTOPStop processorNone0x00/1000////331GSU Control InstructionsSTWStore word data to RAMNone0x3Rm1000////3-87-111-6Data Transfer From register to Game Pak RAMCycles varies due to RAM buffer and programSUBSubtractNone0x6Rn1000****331Arithmetic Operation InstructionsSUBSubtract3E0x6#n2000****662Arithmetic Operation InstructionsSWAPSwap low and high byteNone0x4D/1000/*/*331Byte transfer InstructionsTOSet DregNone0x1Rn1///////331Prefix Register InstructionsUMULTUnsigned multiply3D0x8Rn2000/*/*6 or 86 or 82 or 3Arithmetic Operation InstructionsNumber of cycles depends on CONFIG registerUMULTUnsigned multiply3F0x8#n2000/*/*6 or 86 or 82 or 3Arithmetic Operation Instructions?WITHSet Sreg and DregNone0x2"Rn, ?"?1?????????Prefix Register Instructions?XORBitwise Exclusive Or3D0xCRn2??????????Bitwise Operation Instructions?XORBitwise Exclusive Or3F0xC#n2??????????Bitwise Operation Instructions? Sreg and Dreg For certain instructions, the Sreg and Dreg must be specified before the instruction is run. The Sreg is the "Source Register" and the Dreg is the "Destination Register" - each specified as one of the 16 general purpose registers. Use of the TO, FROM, and WITH instructions specifies the Sreg and Dreg. Bitmap Emulation The Bitmap Emulation function is one of the major acceleration functions of the Super FX. It allows a pixel based shading approach within frame buffer as opposed to a tile based approach in the SNES VRAM. For 3D rendering operations, a fast pixel by pixel shader is necessary. The Super FX provides the framework to plot individual pixels to the frame buffer fast, and then transfer the plotted picture to the SNES VRAM. Fast Multiply The Super FX has 4 multiplication instructions. MULT - Signed 8 bit x Signed 8 bit, with Signed 16 bit result in Dreg. UMULT - Unsigned 8 bit x Unsigned 8 bit, with Unsigned 16 bit result in Dreg. LMULT - Signed 16 bit x Signed 16 bit, with Signed 32 bit result - MSB in Dreg, LSB in R4 FMULT - Signed 16 bit x Signed 16 bit, with Signed 32 bit result. The MULT/UMULT instructions are faster than the LMULT/FMULT instructions. Compiling Super FX Routines Whilst SNES assembly language programs can be compiled using a regular 65c816 compiler, the Super FX assembly language requires a custom compiler. The original compiler used on existing Super FX games has not been released outside the closed development community. An open source compiler called sfxasm is available for compiling Super FX programs. Once compiled, Super FX programs are included in the SNES assembly language program as a binary library. The SNES program then directs the Super FX to use the precompiled program packed into the ROM. Using the Super FX in a SNES Program When the SNES boots up with a Super FX game, the Super FX chip is idle and you don't need to do anything to start the normal SNES routine of loading the ROM and executing code. When the SNES has booted, performed some startup routines and generally is ready, then the Super FX can be activated in your program. Note, for emulators to support Super FX instructions, the $FFD6 byte in the header must be $13, $14, $15, or $1A. The $FFD5 byte should be $20. Initializing The Super FX chip should be initialized before running code. This includes setting the basic config registers. SCBR SCMR CFGR CLSR Choosing the Execution Mode As mentioned before, code can be loaded into the Super FX in 3 different ways - from Game Pak ROM, RAM, and also the 512 byte cache. Depending which way you want to go, there is a slightly different procedure. The advantage of the ROM mode is simplicity at the cost of stopping the SNES CPU while Super FX is processing. The advantage of the RAM mode is to be able to run a large Super FX program whilst the SNES CPU is already busy, but at the cost of having to write the program into Game Pak RAM before running. The advantage of the Cache mode is to run a small program 3 times faster than ROM or RAM modes and additionally while the SNES is busy with both the Game Pak ROM and RAM, but at the cost of loading the program into cache memory before the execution process. Setup - ROM Mode 1. Setup the Program Bank Register (PBR) for where the SFX program starts. 2. Program the program counter (R15) in the Super FX. 3. Give the Super FX exclusive access to the ROM by setting the RON flag in the SFR register. Setup - RAM Mode 1. Transfer the program from ROM into Game Pak RAM using copy routines. 2. Setup the Program Base Register (PBR) for where the SFX program starts. 3. Write to the Super FX program counter (R15). Setup - Cache Mode 1. Transfer the program from ROM into Cache RAM ($3100-$31FF) onwards using copy routines. The programs need to be in blocks of 16 bytes each otherwise the Super FX will not execute the instructions surplus to a 16 byte segment. This also applies for tiny programs under 16 bytes - to get around this, write something into the 16th byte ($310F) 2. Write to the Super FX program counter (R15), this is usually 0. 3. The Super FX program will execute independently of the SNES until it hits a STOP instruction. When it finished, depending if the SFR config interrupt is set, it will generate an interrupt (IRQ) on the SNES. If the interrupt is masked then the Super FX will go to idle mode and wait for the next command from the SNES to start execution. Starting Processing Processing starts when the Super FX notices that the SNES has written to its program counter register (R15). Stopping Processing The Super FX can be stopped in one of two ways - by executing a STOP instruction in the Super FX's program, or from the SNES by writing a "0" to the GO flag in the Super FX's SFR register. Interrupt on Stop The Super FX triggers IRQ on the SNES side when it reads a Super FX STOP instruction. It is possible to mask the interrupt by setting the IRQ bit in the SFR register. If interrupt is not masked, to figure out if it is a screen blanking interrupt or the Super FX, check the IRQ flag bit in the SFR register.