360 Assembly/360 Instructions/ALR

__TOC__ ALR - Add Logical Register - Opcode 1E Format ALR 2,1 The specific syntax is ALR target register, source register. RR Instruction (2 bytes)Byte 1Byte 2target registersource register(8 bits)Opcode1E(4 bits) 0..F(4 bits)0..F The first argument is a target register which value is affected by the instruction. The second argument is the source value register. Availability The ALR instruction is available on all models of the 360, 370 and z/System. Operation The ALR instruction reads 32-bit integer value from the register specified by the second argument and adds it to the value of the register specified by the first argument. The least significant 32 bits of the 33-bit result sum is placed to the target register. The Condition Code field in the Program Status Word is changed according to the resulting value (sum), treated as unsigned integer (see below). As this is a 32-bit instruction, on the zSystem, the high 32 bits of the register are unaffected. Condition Codes The least significant bit of CC field of the PSW is set if sum is not zero and cleared otherwise. The most significant bit of CC field of the PSW keeps carry bit (i.e. the most significant bit of the 33-bit sum). Exceptions and Faults None. Notes The AL and ALR instructions are useful to implement adding of integer values longer than 32 bit. In that case, one should use AL or ALR to count all parts of the sum (possibly except the most significant one), and, if CC is 2 or 3 after the adding (i.e. carry have happened), increment the nearest higher part of the sum. Related instructions 16 bit To add half-word see AH To subtract haLF-word, see SH 32-bit To add logical word value from memory, see AL. To add signed value from memory, see A To add signed value from register, see AR To subtract logical value, see SL or SLR. To subtract signed value, see SR, S, Floating Point To add floating-point values, see AE, AER, AD or ADR. Condition Code To check condition code, see BC or BCR. ALGR AP 1D DR 1F SLR