Aros/Platforms/AROS USB support/Platforms/RISC-V support

Introduction OpenSBI is an open-source reference implementation of the RISC-V Supervisor Binary Interface SBI specification. Firmware running at a higher privilege level that initialises hardware and allows lower privilege levels, such as an operating system, to call into it to perform actions such as power-cycling the device or managing CPU cores. With RISC-V, userspace at ‘U’, the kernel at ‘S’ (supervisor) and the firmware at ‘M’ (machine). RISC-V knows 3 privilege levels: M (machine) mode: highest privilege low-level firmware (e.g. OpenSBI), system boot, and security (e.g. secure execution environments) handles critical system traps return to lower-privileged levels using mret instruction S (supervisor) mode: intermediate privilege used by operating system kernels to manage memory and hardware resources restrict direct access to machine-level configuration registers and physical memory protection (PMP) uses Memory Management Unit (MMU) and virtual memory ecall instruction to request kernel services return to U-mode using sret instruction U (user) mode: lowest privilege cannot execute privileged instructions, access physical memory directly without virtual memory translations, or directly alter core control registers user space executing standard applications prevents incorrect or malicious application code from interfering with other running programs or the operating system itself Thus ‘S’ and ‘VS’ refer to the kernel (where ‘VS’ relates to virtual s-mode when virtualisation is in use). QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the qemu-system-riscv64 executable to simulate a 64-bit RISC-V machine, It also supports 64-bit CPUs. Hardware processor resource, resolving crash dumps, dwmac, [], 64bit BeagleBoard BeagleV SiFive's HiFive Premier P550 Eswin EIC7700X SoC with a quad-core SiFive P550 CPU Milk-V Megrez quad-core SiFive P550 CPU 32bit Milk-V Mars StarFive JH7110 SoC VisionFive 2 SBC StarFive JH7110 SoC HiFive1 Rev B FE310-G002 processor, which includes a 32-bit RV32IMAC core Banana Pi BPI-F3 SpaceMiT K1 8-core RISC-V processor Reference Risc-V Boot [] []