360 Assembly/360 Instructions/SR

__TOC__ SR - Subtract Register - Opcode 1B Format SR 2,1 The specific syntax is SR target register, source register. RR Instruction (2 bytes)Byte 1Byte 2target registersource register(8 bits)Opcode1B(4 bits) 0..F(4 bits)0..F The first argument is a target register which value is affected by the instruction. The second argument is the source value register. Availability The SR instruction is available on all models of the 360, 370 and z/System. Operation The SR instruction reads 32-bit integer value from the register specified by the second argument and subtracts it from the value of register specified by the first argument. The register specified by the first argument holds the operation result after the instruction is executed. The Condition Code field in the Program Status Word is changed according to the resulting value. This instruction can also be used with both register arguments being the same in order to clear that register to zero. The same function occurs if both arguments are the same register in the XR instruction. Condition Codes If signed integer overflow occurs, i.e. difference is not between -2**31 and 2**31-1, CC is set to 3. Otherwise, CC is set to 0, 1 or 2, if difference is equal to zero, below zero or above zero accordingly. Exceptions and Faults If signed integer overflow is detected and the bit 36 in PSW is set, operation exception occurs. Related instructions To subtract by double word value from the full 64-bit double word of both registers on the z/Series, see SGR. To subtract by word value from the full 64-bit double word of the other register on the z/Series, see SGFR. To subtract by full 64-bit double word register on the z/Series from a 64-bit double word in memory, see SG. To subtract from full 64-bit double word register on the z/Series from a 32-bit word in memory, see SGF. To subtract by word value from memory, see S. To subtract by half-word value from memory, see SH. To subtract by value and set condition codes according to unsigned arithmetic, or add not most significant part of multi-word integer value, see SL or SLR. To subtract 32-bit word floating-point values, see SE, SER, SD or SDR. To add a 32-bit word integer value, see AR, A, AH, AL or ALR. To check condition code, see BC or BCR. SQXR SRA 1A AR 1C MR