SPARC Assembly/Arithmetic Instructions

Arithmetic Instructions These are the basic operations used for addition, subtraction, and multiplication. Note that any of these arithmetic instructions may take a register or an immediate value as the op2 parameter. All other parameters (rd and rs1 must be registers). add Adds rs1 and op2, and stores result in rd. addcc Same as above, except that it sets the condition codes. sub subtracts op2 from rs1, and stores the difference in rd subcc same as above, except that it sets the condition codes. mulcc Performs a single step in the multiplication operation. Stores partial results in register Y. Complete multiplication algorithms are discussed in more detail later. Extended Precision These instructions account for the carry bit setting, so that large numbers (larger then the machine word) can be virtually manipulated as a single entity. addx Performs extended addition (adds two operands and carry bit), and stores result in rd. addxcc Same as above, but sets the condition codes. subx Performs extended subtractions (subtracts op2 and C from rs1) and stores result in rd. subxcc same as above, but sets the condition codes. Tagged Instructions tsubcc tsubcctv taddcc taddcctv Y Register These operations affect the Y register. rdy reads the contents of the Y register in to the rd destination register wry exclusively ORs the rs1 and op2 values, and stores that result in the Y register. Logic Instructions and performs the bitwise AND of rs1 and op2, and stores the result in rd. andcc same as above, sets the condition codes. or performs the bitwise OR of rs1 and op2, and stores the result in rd. orcc same as above, sets the condition codes. xor performs the bitwise XOR, between rs1 and op2. stores the result in rd. xorcc same as above, sets the condition codes. xnor performs the bitwise XNOR between rs1 and op2. puts result in rd. xnorcc same as above, sets condition codes. Inverted Logic Operations andn ANDs rs1 and the bitwise inverse of op2. stores result in rd. andncc same as above, sets condition codes. orn ORs rs1 and the bitwise inverse of op2. stores the result in rd. orncc same as above, sets the condition codes. Shift Instructions sll performs the logical left-shift of rs1. Shift amount is according to value of op2. result is stored in rd. srl performs the logical right-shift of rs1. Shift amount is the value of op2. stores the result into rd. sra performs the arithmetic right-shft of rs1. shift amount is the value of op2. stores the result in rd.