Programmable Logic/Verilog Tasks

Tasks in Verilog "task" A task is enabled from a statement that defines the argument values to be passed to the task and the variables that will receive the results. Control is passed back to the enabling process after the task has completed. Thus, if a task has timing controls inside it, then the time of enabling can be different from the time at which control is returned. A task can enable other tasks, which in turn can enable still other tasks—with no limit on the number of tasks enabled. Regardless of how many tasks have been enabled, control does not return until all enabled tasks have completed. Using Tasks [Task_name]([variable list]); Calling Tasks Defining a T ask The following is the syntax for defining tasks: Syntax 9-1: Syntax for <task> Task and function declarations specify the following: local variables I/O ports registers times integers real events These declarations all have the same syntax as for the corresponding declarations in a module definition. If there is more than one output, input, and inout port declared in a task these must be enclosed within a block. <task> = task <name_of_task> ; <tf_declaration>* <statement_or_null> endtask <name_of_task> = <IDENTIFIER> <tf_declaration> = <parameter_declaration> ||= <input_declaration> ||= <output_declaration> ||= <inout_declaration> ||= <reg_declaration> ||= <time_declaration> ||= <integer_declaration> ||= <real_declaration> ||= <event_declaration>