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VHDL for FPGA Design/4-Bit Multiplier
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Design of 4×4-Bit Multiplier VHDL Code
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity Multiplier_VHDL is
port
(
Nibble1, Nibble2: in std_logic_vector(1 downto 0);
Result: out std_logic_vector(2 downto 0)
);
end Multiplier_VHDL;
architecture Behavioral of Multiplier_VHDL is
begin
Result <= std_logic_vector(unsigned(Nibble1) * unsigned(Nibble2));
end Behavioral;
Simulation Waveform
Image:Multi final.png
fi:VHDL-kieli FPGA-suunnittelussa/4-bittinen kertolaskupiiri