The Linux Kernel/Multitasking/Architectures

Architectures Linux CPU architectures refer to the different types of central processing units (CPUs) that are compatible with the Linux operating system. Linux is designed to run on a wide range of CPU architectures, which allows it to be utilized on various devices, from smartphones to servers and supercomputers. Each architecture has its own unique features, advantages, and design considerations. Architectures are classified by family (e.g. x86, ARM), Word (computer architecture) word or Integer_(computer_science)#Long_integer long int size (e.g. CONFIG_32BIT, CONFIG_64BIT). Some functions with different implementations for different CPU architectures: do_boot_cpu > start_secondary > cpu_init setup_arch, start_thread, get_current, current ⚲ API BITS_PER_LONG, __BITS_PER_LONG, ⚙️ Internals arch – architecture-specific code 📖 References CPU Architectures arch x86 CONFIG_X86 arch/x86 – x86 architecture support arch/x86/kernel – core (SMP boot, traps, IRQ, Time Stamp Counter TSC, reboot), x86 Topology arch/x86/topology.html arch/x86/kernel/apic – Advanced Programmable Interrupt Controller APIC (local APIC, I/O APIC, IPI delivery) arch/x86/kernel/cpu/bugs.c – CPU vulnerability mitigations, see Security arch/x86/kernel/cpu/mce – Machine-check exception handling arch/x86/kernel/cpu/microcode – The Linux Microcode Loader arch/x86/microcode.html arch/x86/kernel/cpu/mtrr – Memory type range register MTRR driver arch/x86/mm – Translation lookaside buffer TLB, Page attribute table PAT, Memory type range register MTRR, Secure Memory Encryption SME, see Memory arch/x86/entry – syscall and interrupt entry points, see Syscalls arch/x86/boot – boot protocol and early setup, x86 Feature Flags arch/x86/cpuinfo.html, see Booting arch/x86/kvm – Kernel-based Virtual Machine KVM, see Virtualization arch/x86/crypto – AES instruction set AES-NI, SHA, CRC, see Crypto arch/x86/coco – confidential computing (Trust Domain Extensions TDX, AMD SEV SEV) arch/x86/events – Hardware performance counter PMU drivers for perf, see Perf arch/x86/net – x86 BPF JIT compiler, see eBPF arch/x86/xen – Xen paravirtualization arch/x86/hyperv – Hyper-V support drivers/platform/x86 – x86 platform drivers 1 perf-intel-pt – support for Intel Processor Trace within perf CPU feature flags CPU features detected at boot from CPUID, visible in /proc/cpuinfo flags. arch/x86/include/asm/cpufeatures.h arch/x86/include/generated/asm/cpufeaturemasks.h 4 cpuid – x86 CPUID device tools/arch/x86/kcpuid – kernel CPUID dumping tool cd tools/arch/x86/kcpuid && make && ./kcpuid --detail | grep $'^\t' – list local CPU features with descriptions https://gitlab.com/x86-cpuid.org/x86-cpuid-db – CPUID feature database Extended features (newest first): Compute: Advanced Matrix Extensions AMX – Advanced Matrix Extensions for AI/ML workloads, 2023 AVX-512 – 512-bit SIMD, 2016 Security: X86_FEATURE_SHSTK – CET Shadow Stack, control-flow integrity, 2020 X86_FEATURE_IBT – CET Indirect Branch Tracking, 2020 X86_FEATURE_UMIP – User-Mode Instruction Prevention, 2017 X86_FEATURE_PKU – Memory protection key Memory Protection Keys for user pages, 2016 Memory management: X86_FEATURE_LA57 – 5-level paging, 57-bit virtual addresses (128 PB), 2019 Timing: X86_FEATURE_ART – Always Running Timer, fixed TSC/crystal ratio for PTP, 2016 X86_FEATURE_TSC_DEADLINE_TIMER – APIC timer in TSC-deadline mode, 2011 Virtualization: X86_FEATURE_FRED – Flexible Return and Event Delivery, replaces Interrupt descriptor table IDT, 2025 Additional baseline not in X86-64#Microarchitecture levels microarchitecture levels but present on all post-2017 CPUs: Intel ADX adx – multi-precision arithmetic AES instruction set aes – hardware AES acceleration apic – APIC on-chip clflush – CLFLUSH instruction clflushopt – optimized cache line flush constant_tsc – TSC ticks at constant rate across P-states and C-states de – Debugging Extensions FSGSBASE fsgsbase – direct FS/GS base access from userspace ht – Hyper-threading invpcid – selective PCID TLB invalidation mca – Machine Check Architecture mce – Machine-check exception msr – Model-Specific Registers (RDMSR/WRMSR) mtrr – Memory type range register Memory Type Range Registers nonstop_tsc – TSC does not stop in C-states NX bit nx – No-execute page protection pat – Page attribute table Process-context identifier pcid – avoids full TLB flush on context switch pse36 – Page Size Extension (36-bit) RDRAND rdrand – hardware random number generator RDRAND rdseed – hardware random seed rdtscp – RDTSCP instruction sep – SYSENTER/SYSEXIT Supervisor Mode Access Prevention smap – blocks kernel accessing user pages Supervisor Mode Execution Prevention smep – blocks kernel executing user pages tsc – Time Stamp Counter x2apic – extended APIC, supports >256 CPUs X86-64#Microarchitecture levels x86-64-v4 – AVX-512, ~2017 x86-64-v3 – AVX/AVX2, FMA, BMI, ~2015 x86-64-v2 – SSE3/SSSE3/SSE4, POPCNT, ~2009 x86-64-v1 – SSE/SSE2, required by kernel Can be disabled at compile time: CENTAUR_MCR, CYRIX_ARR, ENQCMD, FRED, K6_MTRR, LAM, SEV_SNP, SGX, TDX_GUEST, USER_SHSTK, VME, XENPV VT-x VMX / AMD-V SVM – hardware virtualization, 2005/2006 📖 References x86-specific arch/x86 x86_64 Support arch/x86/x86_64 architecture-specific initialization https://lwn.net/Kernel/Index/#Architectures-x86 ARM CONFIG_ARM – 32-bit, CONFIG_ARM64 – 64-bit (AArch64) arch/arm – 32-bit ARM arch/arm64 – 64-bit ARM (AArch64) ARM big.LITTLE – heterogeneous multiprocessing, see EAS 📖 References ARM Architecture arch/arm ARM64 Architecture arch/arm64 Memory Tagging Extension (MTE) arch/arm64/memory-tagging-extension.html – hardware memory safety Scalable Vector Extension (SVE) arch/arm64/sve.html https://lwn.net/Kernel/Index/#Architectures-ARM