360 Assembly/360 Instructions

When the System/360 ("360") was introduced in 1964, there were five instruction formats: RR, RS, RX, SI, and SS. An instruction's format was determined by the first two bits of its operation code ("opcode"), which is the instruction's first eight bits. The first 2-bits are as follows: 00 (opcodes 00 to 3F/0 to 63 (decimal); RR instruction, generally two registers), 2 bytes 01 (opcodes 40 to 7F/64 to 127 (decimal); RX instruction, one register and one address calculated using a base register, an index register, and a displacement of 0 to 4095 bytes), 4 bytes 10 (opcodes 80 to BF/128 to 191 (decimal); RS or SI instruction), 4 bytes (An RS instruction was generally one register and a storage location address.) (An SI instruction was generally one register, one immediate value, and a storage location address.), 4 bytes 11 (opcodes C0 to FF/192 to 255 (decimal); SS instruction, one or two length operands and two storage addresses), 6 byes In order to encourage the expansion of IBM mainframes into more and more uses, the capabilities of their processors were enhanced with new instruction formats, allowing for additional functionality at the machine code level. Currently, there are many instruction formats now available on all mainframe models: the 360, System/370 ("370" or "S/370"), ESA/390 ("390"), and z/System ("Z"). Each instruction format, along with a breakdown and explanation of the format, is provided in the table below. Notes: Under "Availability," unless "all" is specified, it is available on certain models, namely: "370" indicates an instruction is available on 370 and later models (370,390, and z/System); "ESA/390" indicates that an instruction is available on 390 and z/System; and "Z" indicates an instruction is available on z/System only. However, despite the listed availability of a particular instruction format, the availability of a specific instruction of that format may be further restricted. A "base-displacement" address is described as "B1, D1" where a base-displacement address is used or as either "B2, D2" or "B2, D2, X2" where an index register is also used (the address is indexed). If a base-displacement address is not indexed, the X2 field on the second operand is not used. The B or X values refer to a 4-bit register value from 0 to 15, and the D value is an unsigned, 12-bit displacement address. Instructions take a multiple of two bytes, and are two, four or six bytes in length. <td colspan="1" style="vertical-align: top;"> <td colspan="10" style="vertical-align: top;">Format Breakdown InstructionFormat First Halfword Second Halfword Third Halfword Availability Size inBytes Explanation Bits (0-7) (8-11) (12-15) (16-19) (20-23) (24-27) (28-31) (32-35) (36-39) (40-47) I OpCode I silver All 2 The I-type instruction is a subformat of the RR instruction format where the low eight bits are used as an immediate value from 0 to 255. The only instruction of this subformat is the SVC instruction. E OpCode silver ESA/390 2 E, Modified RR instruction, 16-bit opcode, no arguments. IE OpCode / / / / / / / / I1 I2 silver Z 4 IE, 16-bit opcode, two immediate values and eight unused bits. MII OpCode M1 RI2 RI3 Z 6 MII, consisting of a mask and two immediate values. RIE OpCode R1 / / / / I2 M3 / / / / Addit- ional Op Code Z 6 RIE-a, consisting of a register, a 16-bit immediate value, a mask, four unused bits and an additional opcode. OpCode R1 R2 RI4 M3 / / / / Addit- ional Op Code Z 6 RIE-b, consisting of two registers, a mask, two 16-bit immediate values, four unused bits and an additional opcode. OpCode R1 M3 RI4 I2 Addit- ional Op Code Z 6 RIE-c, consisting of a register, an immediate value, a mask, a register, and an additional opcode. OpCode R1 R3 I2 / / / / / / / / Addit- ional Op Code Z 6 RIE-d, consisting of an instruction, two registers, a 16-bit immediate value, eight unused bits and an additional opcode. OpCode R1 R3 RI4 / / / / / / / / Addit- ional Op Code Z 6 RIE-e, consisting of an instruction, two registers, a register, eight unused bits and an additional opcode. OpCode R1 R2 I3 I4 I5 Addit- ional Op Code Z 6 RIE-f, consisting of an instruction, two registers, three immediate values and an additional opcode. OpCode R1 M3 I2 / / / / / / / / Addit- ional Op Code Z 6 RIE-g, consisting of an instruction, a register, a mask, a 16-bit immediate value, eight unused bits and an additional opcode. RIL OpCode R1 Addit- ional Op Code I2 ESA/390 6 RIL-a, consisting of an instruction with a register, an additional opcode, and an additional 32-bit immediate value. OpCode R1 Addit- ional Op Code RI2 Z 6 RIL-b, consisting of an instruction with a register, an additional opcode, and a register. OpCode M1 Addit- ional Op Code RI2 Z 6 RIL-c, consisting of an instruction with a mask, an additional opcode, and a register. RIS OpCode R1 M3 B4 D4 I2 Addit- ional Op Code Z 6 RIS, consisting of an instruction with a register, a mask, a base-displacement address, an additional 8-bit immediate value, and an additional opcode. RR OpCode R1 R2 All 2 RR Instructions use two registers for the arguments. RRD OpCode R1 / / / / R3 R2 silver Z 4 RRD, consisting of a register, four unused bits and two registers. RRE OpCode / / / / / / / / R1 R2 silver S/370 4 RRE, consisting of two registers and eight unused bits. RRF1 OpCode R1 / / / / R3 R2 silver ESA/390 4 RRF, consisting of 3 registers and 4 unused bits. RRF2 OpCode M3 / / / / R1 R2 silver ESA/390 4 RRF, consisting of a 16-bit opcode, 2 registers, a mask and 4 unused bits. RRF3 OpCode R3 M4 R1 R2 silver ESA/390 4 RRF, consisting of a 16-bit opcode, three registers and a 4-bit mask. RRR OpCode R3 / / / / R1 R2 silver ESA/390 4 RRR consisting of a 16-bit opcode, four unused bits and three registers. RRS OpCode R1 R2 B4 D4 M3 / / / / Addit- ional Op Code Z 6 RRS consisting of two registers, a base-displacement address, a mask, four unused bits and an additional opcode. RS1 OpCode R1 R3 B2 D2 silver All 4 RS, consisting of two registers and an unindexed base-displacement address to reference a single string. RS2 OpCode R1 M3 B2 D2 4 RS, consisting of one register, a 4-bit mask and an unindexed base-displacement address to reference a single string. RSE OpCode R1 R3 B2 D2 / / / / / / / / Addit-ional Op Code ESA/390 6 RSE, consisting of an expanded RS format instruction of with an additional opcode and eight unused bits, one register, and an unindexed base-displacement address to reference a single string. OpCode R1 M3 B2 D2 / / / / / / / / OpCd ESA/390 6 RSE, consisting of an expanded RS format instruction of with an additional op code and 8 unused bits, a 4-bit mask, and an unindexed base-displacement address to reference a single string. RSL OpCode L1 / / / / B2 D2 / / / / / / / / OpCd ESA/390 6 RSL, consisting of an expanded RS format instruction with an additional opcode and 12 unused bits. RSI OpCode R1 R3 I2 ESA/390 4 RSI, consisting of an instruction with two registers and a 16-bit immediate value. RI OpCode R1 Addit-ional Op Code I2 ESA/390 4 RI, consisting of an instruction with a register, an additional opcode, and an additional 16-bit immediate value. OpCode R1 Addit-ional Op Code RI2 Z 4 RI, consisting of an instruction with a register, an additional opcode, and an additional signed binary integer value. OpCode M1 Addit-ional Op Code RI2 Z 4 RI, consisting of an instruction with a mask, an additional opcode, and an additional signed binary integer value. RX OpCode R1 X2 B2 D2 All 4 RX Instructions use one register and an index register plus base-displacement address. RXE OpCode R1 X2 B2 D2 / / / / / / / / Addit-ional Op Code ESA/390 6 RXE, consisting of an expanded RX format instruction with an additional opcode and eight unused bits. RXF OpCode R3 X2 B2 D2 R1 / / / / Addit- ional Op Code ESA/390 6 RXF, consisting of an expanded RX format instruction with an additional register, an additional opcode and four unused bits. RXY OpCode R1 X2 B2 DL2 DH2 Addit-ional Op Code ESA/390 6 RXY-a (like RXE), consisting of an expanded RX format instruction with an additional eight displacement bits and opcode. OpCode M1 X2 B2 DL2 DH2 Addit-ional Op Code ESA/390 6 RXY-b (like RXY-a), consisting of an instruction with a mask and an index register plus base-displacement address, an additional eight displacement bits and opcode. S OpCode B2 D2 S/370 4 S, containing of a 16-bit opcode, and a single unindexed base-displacement address. SI OpCode I2 B1 D1 All 4 SI, consisting of an 8-bit immediate value and an unindexed base-displacement address. SS OpCode L B1 D1 B2 D2 All 6 SS, instructions which use a 1 byte length, and two unindexed base-displacement addresses to reference two strings with a length of up to 256 bytes. OpCode L1 L2 B1 D1 B2 D2 6 SS, instructions which use two unindexed base-displacement addresses to reference two strings each with their own specified length of up to 16 bytes. OpCode R1 R3 B1 D1 B2 D2 6 SS, instructions which use two registers and two unindexed base-displacement addresses to reference two strings. SSE OpCode B1 D1 B2 D2 S/370 6 SSE, containing a 16-bit opcode and two unindexed base-displacement addresses. SSF OpCode R3 Addit-ional Op Code B1 D1 B2 D2 Z 6 SSF, consisting of a register, an additional opcode, and two unindexed base-displacement addresses. VRI OpCode V1 / / / / I2 M3 RXB Addit-ional Op Code Z 6 VRI-a, consisting of a vector, an immediate 2-byte value, a mask, and an additional opcode. OpCode V1 / / / / I2 I3 M4 RXB Addit-ional Op Code Z 6 VRI-b, consisting of an instruction, a vector, two immediate byte values, a mask, and an additional opcode. OpCode V1 V3 I2 M4 RXB Addit-ional Op Code Z 6 VRI-c, consisting of an instruction, two vectors, an immediate 2-byte value, a mask, and an additional opcode. OpCode V1 V2 V3 / / / / I4 M5 RXB Addit-ional Op Code Z 6 VRI-d, consisting of an instruction, three vectors, an immediate byte value, a mask, and an additional opcode. OpCode V1 V2 I3 M5 M4 RXB Addit-ional Op Code Z 6 VRI-e, consisting of an instruction, two vectors, an immediate 12-bit value, tow masks, and an additional opcode. OpCode V1 V2 V3 / / / / M5 I4 RXB Addit-ional Op Code Z 6 VRI-f, consisting of an instruction, three vectors, a mask, an immediate byte value, and an additional opcode. OpCode V1 V2 I4 M5 I3 RXB Addit-ional Op Code Z 6 VRI-g, consisting of an instruction, twµ vectors, an immediate byte value, a mask, another immediate byte value, and an additional opcode. OpCode V1 / / / / I2 I3 RXB Addit-ional Op Code Z 6 VRI-h, consisting of an instruction, a vector, an immediate 2-byte value, a 4-bit immediate value, and an additional opcode. OpCode V1 R2 / / / / / / / / M4 I3 RXB Addit-ional Op Code Z 6 VRI-i, consisting of an instruction, a vector, a register, a mask, an immediate byte value, and an additional opcode. VRR OpCode V1 V2 / / / / / / / / M5 M4 M3 RXB Addit-ional Op Code Z 6 VRR-a, consisting of an instruction, two vectors, three mask, and an additional opcode. OpCode V1 V2 V3 / / / / M5 / / / / M4 RXB Addit-ional Op Code Z 6 VRR-b, consisting of an instruction, three vectors, two masks, and an additional opcode. OpCode V1 V2 V3 / / / / M6 M5 M4 RXB Addit-ional Op Code Z 6 VRR-c, consisting of an instruction, three vectors, three masks, and an additional opcode. OpCode V1 V2 V3 M5 M6 / / / / V4 RXB Addit-ional Op Code Z 6 VRR-d, consisting of an instruction, three vectors, three mask, a vector, and an additional opcode. OpCode V1 V2 V3 M6 / / / / M5 V4 RXB Addit-ional Op Code Z 6 VRR-e, consisting of an instruction, three vectors, an immediate byte value, a mask, and an additional opcode. OpCode V1 R2 R3 / / / / / / / / / / / / / / / / RXB Addit-ional Op Code Z 6 VRR-f, consisting of an instruction, a vector, two registers, and an additional opcode. OpCode / / / / V1 / / / / / / / / / / / / / / / / / / / / RXB Addit-ional Op Code Z 6 VRR-g, consisting of an instruction, a vector, and an additional opcode. OpCode / / / / V1 V2 / / / / M3 / / / / / / / / RXB Addit-ional Op Code Z 6 VRR-h, consisting of an instruction, two vectors, a mask, and an additional opcode. OpCode R1 V2 / / / / / / / / M3 M4 / / / / RXB Addit-ional Op Code Z 6 VRR-i, consisting of an instruction, a register, a vector, a register, two masks, and an additional opcode. VRS OpCode V1 V3 B2 D2 M4 RXB Addit-ional Op Code Z 6 VRS-a, consisting of two vectors, an unindexed base-displacement address, a mask, and an additional opcode. OpCode V1 R3 B2 D2 M4 RXB Addit-ional Op Code Z 6 VRS-b, consisting of an instruction, a vector, a register, an unindexed base-displacement address, a mask, and an additional opcode. OpCode R1 V3 B2 D2 M4 RXB Addit-ional Op Code Z 6 VRS-c, consisting of an instruction, a register, a vector, an unindexed base-displacement address, a masks, and an additional opcode. OpCode / / / / R3 B2 D2 V1 RXB Addit-ional Op Code Z 6 VRS-d, consisting of a register, an unindexed base-displacement address, a vector, and an additional opcode. VRV OpCode V1 V2 B2 D2 M3 RXB Addit-ional Op Code Z 6 VRV, consisting of an instruction, two vectors, an unindexed base-displacement address, a mask, and an additional opcode. VRX OpCode V1 X2 B2 D2 M3 RXB Addit-ional Op Code Z 6 VRX, consisting of an instruction, a vector, an index, an unindexed base-displacement address, a mask, and an additional opcode. VSI OpCode I3 B2 D2 V1 RXB Addit-ional Op Code Z 6 VSI, consisting of an instruction, an immediate byte value, an unindexed base-displacement address, a vector, and an additional opcode. All instructions must be aligned to an even address. Attempts to create an instruction at an odd address will be flagged as an error by the assembler; an attempt to branch to an odd address will result in an address exception. There are four instruction set architectures: 360 instructions are those which were part of the original IBM 360 mainframe instruction set architecture and are shown on the table below in this color: [       ]. Except for instructions marked "360 only," these instructions work on all models. 370 instructions were added with the creation of the IBM 370 and are shown on the table below in this color: [       ]. They are only available on 370- and higher-series machines and will not work (and will "throw an exception") if they are attempted to be executed on a 360. Instructions marked "370 only" will also throw an exception on the 390 or Z. Instructions marked "370 only" and "390 only" will throw an exception on the z/System. ESA/390 instructions were created for the 390 and are shown on the table below in this color: [       ]. They are only available on ESA/390 and z/System mainframes and will throw an exception if they are attempted to be executed on a 360 or S/370. Instructions marked "390 Only" will throw an exception on the z/System. z/System instructions were created after the 370 and 390 and are shown on the table below in this color: [       ]. They will throw an exception on 360, 370, or 390 hardware and work only on z/System mainframes. In general, there are seven classes of instructions: Branch Instructions, which jump from one part of a program to another Data Transfer Instructions, which move data from one part of memory (including registers) Control Flow Instructions, which make changes in the scope of execution of a program Arithmetic Instructions, which do computations Logic Instructions, which make comparisons Shift and Rotate Instructions, which move bits right or left, Privileged Instructions, used by the operating system or other programs having special permission, primarily to do input/output or to control the operations of the machine, and Other Instructions, instructions not otherwise classified Additionally, the S/370 and S/390 had an optional Vector Facility, whose instruction opcodes can be seen in the table below, beginning with A4 hexadecimal. Support for the Vector Facility was discontinued with the z/Architecture; however, the z13 reintroduced vector instructions, albeit a new set of vector instructions with incompatible opcodes from the old 370/390 Vector Facility. (The new z13 vector instructions are not currently in the table.) The table below lists specific instructions available on the four instruction set architectures. The table can be sorted by column. To do so, click on the symbol at the top of a column. The numeric value of opcodes listed is shown in hexadecimal only. Opcode(Hex) Mnemonic Description Instruction Format Instruction Class Instruction Set Architecture00 The opcode 00 will always throw an invalid op-code exception on all models of all machine types. Some programmers will use it to test error-handling, and some operating systems use it to catch "runaway" programs, ones that have continued executing past the end of the code of the program.0101 PR Program Return E C 0102 UPT Update Tree E D 0104 PTFF Perform Timing Facility Function E C 0105 CMSG Clear Message E D 0106 TMSG Test Message E D 0107 SCKPF Set (TOD) Clock Programmable Field E C 0108 TMPS Test Message Path State E D 0109 CMPS Clear Message Path State E D 010A PFPO Perform Floating Point Operation E D 010B TAM Test Addressing Mode E C 010C SAM24 Set Addressing Mode (to 24 bits) E C 010D SAM31 Set Addressing Mode (to 31 bits) E C 010E SAM64 Set Addressing Mode (to 64 bits) E C 01FF TRAP2 Trap E C 04 SPM Set Program Mask RR O 05 BALR Branch And Link Register RR B 06 BCTR Branch on CounT Register RR B 07 BCR Branch on Condition Register RR B 070 NOPR No Operation Register RR B 07F BR Branch Register (Unconditional) RR B 08 SSK Set Storage Key RR P 360 Only 09 ISK Insert Storage Key RR P 360 Only 0A SVC SuperVisor Call I C 0B BSM Branch and Set Mode RR B 0C BASSM Branch and Save and Set Mode RR B 0D BASR Branch And Save Register RR B 0E MVCL MoVe Character Long RR D 0F CLCL Compare Logical Character Long RR L 10 LPR Load Positive Register RR D 11 LNR Load Negative Register RR D 12 LTR Load and Test Register RR D 13 LCR Load and Complement Register RR A 14 NR aNd Register RR A 15 CLR Compare Logical Register RR L 16 OR Or Register RR A 17 XR eXclusive-or Register RR A 18 LR Load Register RR D 19 CR Compare Register RR L 1A AR Add Register RR A 1B SR Subtract Register RR A 1C MR Multiply Register RR A 1D DR Divide Register RR A 1E ALR Add Logical Register RR A 1F SLR Subtract Logical Register RR A 20 LPDR Load Positive (Long) RR D 21 LNDR Load Negative RR D 22 LTDR Load and Test RR D 23 LCDR Load Complement (Long) RR D 24 HDR Halve RR A 25 LDXR Load Rounded RR D 25 LRDR Load Rounded RR D 360 Only 26 MXR Multiply RR A 27 MXDR Multiply RR A 28 LDR Load RR D 29 CDR Compare Double Reg. RR L 2A ADR Add Double Register RR A 2B SDR Subtract Double Reg. RR A 2C MDR Multiply Double Reg. RR A 2D DDR Divide Double Reg. RR A 2E AWR Add Unnormalized RR A 2F SWR Subtract Unnormalized RR A 30 LPER Load Positive (Short) RR D 31 LNER Load Negative RR D 32 LTER Load and Test RR D 33 LCER Load Complement (Short) RR D 34 HER Halve RR A 35 LEDR Load Rounded RR D 35 LRER Load Rounded RR D 360 Only 36 AXR Add Normalized RR A 37 SXR Subtract Normalized RR A 38 LER Load RR D 39 CER Compare RR L 3A AER Add Normalized RR A 3B SER Subtract Normalized RR A 3C MER Multiply Normalized RR A 3D DER Divide Normalized RR A 3E AUR Add Unnormalized RR A 3F SUR Subtract Unnormalized RR A 40 STH STore Halfword RX D 41 LA Load Address RX D 42 STC STore Character RX D 43 IC Insert Character RX D 44 EX EXecute RX D 45 BAL Branch And Link RX B 46 BCT Branch on CounT RX B 47 BC Branch on Condition RX B 470 NOP No Operation RX B 471 BO Branch on Overflow/Ones RX B 472 BH Branch (a High) RX B 472 BP Branch on Plus RX B 474 BL Branch (a Low) RX B 474 BM Branch on Minus/Mixed RX B 477 BNE Branch Not Equal RX B 477 BNZ Branch Not Zero RX B 478 BE Branch (a Equal b) RX B 478 BZ Branch on Zero RX B 47B BNL Branch (a Not Low) RX B 47B BNM Branch Not Minus RX B 47D BNH Branch Not High RX B 47D BNP Branch Not Plus RX B 47E BNO Branch Not Ones RX B 47F B Branch (unconditional) RX B 48 LH Load Halfword RX D 49 CH Compare Halfword RX L 4A AH Add Halfword RX A 4B SH Subtract Halfword RX A 4C MH Multiply Halfword RX A 4D BAS Branch And Save RX B 4E CVD ConVert to Decimal RX D 4F CVB ConVert to Binary RX D 50 ST STore RX D 51 LAE Load Address Extended RX D 54 N aNd RX A 55 CL Compare Logical RX L 56 O Or RX A 57 X eXclusive or RX A 58 L Load RX D 59 C Compare RX L 5A A Add RX A 5B S Subtract RX A 5C M Multiply RX A 5D D Divide RX A 5E AL Add Logical RX A 5F SL Subtract Logical RX A 60 STD Store Double RX D 67 MXD Multiply Double RX A 68 LD Load Double RX D 69 CD Compare Double RX L 6A AD Add Double normalized RX A 6B SD Subtract Double normalized RX A 6C MD Multiply Double RX A 6D DD Divide Double RX A 6E AW Add unnormalized Word RX A 6F SW Subtract unnormalized Word RX A 70 STE Store short RX D 71 MS Multiply Single RX D 78 LE Load short RX D 79 CE Compare short RX L 7A AE Add normalized short RX A 7B SE Subtract normalized short RX A 7C MDE Multiply short RX A 7C ME Multiply short RX A 7D DE Divide short RX A 7E AU Add Unnormalized short RX A 7F SU Subtract Unnormalized short RX A 80 SSM Set System Mask SI P 82 LPSW Load Program Status Word S P 83 DIAGNOSE Diagnose[1] RX P 84 WRD Write Direct RX P 360 Only 85 RDD Read Direct RX P 360 Only 84 BRXH Branch Relative on indeX High RSI B 84 JXH Jump on indeX High RSI B 85 BRXLE Branch Relative on indeX Low or Equal RSI B 85 JXLE Jump on indeX Low or Equal RSI B 86 BXH Branch on indeX High RS B 87 BXLE Branch on indeX Low or Equal RS B 88 SRL Shift Right single Logical RS S 89 SLL Shift Left Logical RS S 8A SRA Shift Right Arithmetic RS S 8B SLA Shift Left Arithmetic RS S 8C SRDL Shift Right Double Logical RS S 8D SLDL Shift Left Double Logical RS S 8E SRDA Shift Right Double Arithmetic RS S 8F SLDA Shift Left Double Arithmetic RS S 90 STM STore Multiple RS D 91 TM Test under Mask SI L 92 MVI MoVe Immediate SI D 93 TS Test and Set SI L 94 NI aNd Immediate SI D 95 CLI Compare Logical Immediate SI L 96 OI Or Immediate SI D 97 XI eXclusive-or Immediate SI D 98 LM Load Multiple RS D 99 TRACE Trace RS P 9A LAM Load Access Multiple RS D 9B STAM Store Access Multiple RS D 9C SIO Start I/O SI P 360 Only 9C00 SIO Start I/O SI P 9C01 SIOF Start I/O Fast release SI P 9C00 RIO Resume I/O SI P 9D TIO Test I/O SI P 360 Only 9D00 TIO Test I/O SI P 370 Only 9D01 CLRIO CLeaR I/O SI P 370 Only 9E HIO Halt I/O SI P 360 Only 9E00 HIO Halt I/O SI P 370 Only 9E01 HDV Halt DeVice SI P 370 Only 9F TCH Test CHannel SI P 360, 370 Only 9F00 TCH Test CHannel SI P 390 & Z 9F01 CLRCH Clear CHannel SI P B258 BSG Branch in Subspace Group RRE B A4-- Vector Instructions RI-a O 370 and 390 Only A400 VAE Add Exponential (Vector) RI-a O 370 and 390 Only A401 VSE Subtract (Vector) RI-a O 370 and 390 Only A402 VME Multiply (Vector) RI-a O 370 and 390 Only A403 VDE Divide (Vector) RI-a O 370 and 390 Only A404 VMAE (Vector) RI-a O 370 and 390 Only A405 VMSE (Vector) RI-a O 370 and 390 Only A406 VMCE (Vector) RI-a O 370 and 390 Only A407 VACE ACcumulate Exponential (Vector) RI-a O 370 and 390 Only A408 VCE (Vector) RI-a O 370 and 390 Only A409 VL (Vector) RI-a O 370 and 390 Only A40A VLM (Vector) RI-a O 370 and 390 Only A40B VLY (Vector) RI-a O 370 and 390 Only A40D VST (Vector) RI-a O 370 and 390 Only A40E VSTM (Vector) RI-a O 370 and 390 Only A40F VSTK (Vector) RI-a O 370 and 390 Only A410 VAD Add Double (Vector) RI-a O 370 and 390 Only A411 VSD Subtract (Vector) RI-a O 370 and 390 Only A412 VMD Multiply (Vector) RI-a O 370 and 390 Only A413 VDD Divide (Vector) RI-a O 370 and 390 Only A414 VMAD (Vector) RI-a O 370 and 390 Only A414 VMSD (Vector) RI-a O 370 and 390 Only A416 VMCD (Vector) RI-a O 370 and 390 Only A417 VACD ACcumulate Double (Vector) RI-a O 370 and 390 Only A418 VCD (Vector) RI-a O 370 and 390 Only A419 VLD (Vector) RI-a O 370 and 390 Only A41A VLMD (Vector) RI-a O 370 and 390 Only A41B VLYD (Vector) RI-a O 370 and 390 Only A41D VSTD (Vector) RI-a O 370 and 390 Only A41E VSTMD (Vector) RI-a O 370 and 390 Only A41F VSTKD (Vector) RI-a O 370 and 390 Only A420 VA Add (Vector) RI-a O 370 and 390 Only A421 VS Subtract (Vector) RI-a O 370 and 390 Only A422 VM Multiply (Vector) RI-a O 370 and 390 Only A424 VN (Vector) RI-a O 370 and 390 Only A425 VO (Vector) RI-a O 370 and 390 Only A426 VX (Vector) RI-a O 370 and 390 Only A428 VC (Vector) RI-a O 370 and 390 Only A429 VLH (Vector) RI-a O 370 and 390 Only A42A VLINT (Vector) RI-a O 370 and 390 Only A42D VSTH (Vector) RI-a O 370 and 390 Only A443 VSQE (Vector) RI-a O 370 and 390 Only A444 VTAE (Vector) RI-a O 370 and 390 Only A445 VTSE (Vector) RI-a O 370 and 390 Only A453 VSQD (Vector) RI-a O 370 and 390 Only A454 VTAD (Vector) RI-a O 370 and 390 Only A455 VTSD (Vector) RI-a O 370 and 390 Only A480 VAES Add Exponential to Storage (Vector) RI-a O 370 and 390 Only A481 VSES Subtract (Vector) RI-a O 370 and 390 Only A482 VMES Multiply (Vector) RI-a O 370 and 390 Only A483 VDES Divide (Vector) RI-a O 370 and 390 Only A484 VMAES (Vector) RI-a O 370 and 390 Only A485 VMSES (Vector) RI-a O 370 and 390 Only A488 VCES (Vector) RI-a O 370 and 390 Only A490 VADS Add Double to Storage (Vector) RI-a O 370 and 390 Only A491 VSDS Subtract (Vector) RI-a O 370 and 390 Only A492 VMDS Multiply (Vector) RI-a O 370 and 390 Only A493 VDDS Divide (Vector) RI-a O 370 and 390 Only A494 VMADS (Vector) RI-a O 370 and 390 Only A495 VMSDS (Vector) RI-a O 370 and 390 Only A498 VCDS (Vector) RI-a O 370 and 390 Only A4A0 VAS Add (Vector) RI-a A 370 and 390 Only A4A1 VSS Subtract (Vector) RI-a A 370 and 390 Only A4A2 VMS Multuiply (Vector) RI-a A 370 and 390 Only A4A4 VNS (Vector) RI-a O 370 and 390 Only A4A5 VOS (Vector) RI-a O 370 and 390 Only A4A6 VXS (Vector) RI-a O 370 and 390 Only A4A8 VCS (Vector) RI-a O 370 and 390 Only A5-- Vector Instructions RI-a O 370 and 390 Only A500 VAER Add Exponential Register (Vector) RI-a A 370 and 390 Only A501 VSER Subtract (Vector) RI-a A 370 and 390 Only A502 VMER Multiply (Vector) RI-a A 370 and 390 Only A503 VDER (Vector) RI-a O 370 and 390 Only A506 VMCER (Vector) RI-a O 370 and 390 Only A507 VACER ACcumulate Exponential Reg. (Vector) RI-a O 370 and 390 Only A508 VCER (Vector) RI-a O 370 and 390 Only A509 VLR (Vector) RI-a O 370 and 390 Only A50A VLMR (Vector) RI-a O 370 and 390 Only A50B VLZR (Vector) RI-a O 370 and 390 Only A510 VADR Add Double to Register (Vector) RI-a A 370 and 390 Only A511 VSDR Subtract (Vector) RI-a A 370 and 390 Only A512 VMDR Multiply (Vector) RI-a A 370 and 390 Only A513 VDDR Divide (Vector) RI-a A 370 and 390 Only A516 VMCER (Vector) RI-a O 370 and 390 Only A517 VACDR Accumulate Double Register (Vector) RI-a O 370 and 390 Only A518 VCDR (Vector) RI-a O 370 and 390 Only A519 VLDR (Vector) RI-a O 370 and 390 Only A51A VLMDR (Vector) RI-a O 370 and 390 Only A51B VLZDR (Vector) RI-a O 370 and 390 Only A520 VAR Add to Register (Vector) RI-a A 370 and 390 Only A521 VSR Subtract (Vector) RI-a A 370 and 390 Only A522 VMR Multiply (Vector) RI-a A 370 and 390 Only A524 VNR (Vector) RI-a O 370 and 390 Only A525 VOR (Vector) RI-a O 370 and 390 Only A526 VXR (Vector) RI-a O 370 and 390 Only A528 VCR (Vector) RI-a O 370 and 390 Only A540 VLPER (Vector) RI-a O 370 and 390 Only A541 VLNER (Vector) RI-a O 370 and 390 Only A542 VLCER (Vector) RI-a O 370 and 390 Only A543 VSQER (Vector) RI-a O 370 and 390 Only A550 VLPDR (Vector) RI-a O 370 and 390 Only A551 VLNDR (Vector) RI-a O 370 and 390 Only A552 VLCDR (Vector) RI-a O 370 and 390 Only A553 VSQDR (Vector) RI-a O 370 and 390 Only A560 VLPR (Vector) RI-a O 370 and 390 Only A561 VLNR (Vector) RI-a O 370 and 390 Only A562 VLCR (Vector) RI-a O 370 and 390 Only A580 VAEQ Add Exponential (Vector) RI-a A 370 and 390 Only A581 VSEQ Subtract (Vector) RI-a A 370 and 390 Only A582 VMEQ Multiply (Vector) RI-a A 370 and 390 Only A583 VDEQ Divide (Vector) RI-a A 370 and 390 Only A584 VMAEQ (Vector) RI-a O 370 and 390 Only A585 VMSEQ (Vector) RI-a O 370 and 390 Only A588 VCEQ (Vector) RI-a O 370 and 390 Only A589 VLEQ (Vector) RI-a O 370 and 390 Only A58A VLMEQ (Vector) RI-a O 370 and 390 Only A590 VADQ Add Double to Qualified Reg. (Vector) RI-a A 370 and 390 Only A591 VSDQ Subtract (Vector) RI-a A 370 and 390 Only A592 VMDQ Multiply (Vector) RI-a A 370 and 390 Only A593 VDDQ Divide (Vector) RI-a A 370 and 390 Only A594 VMADQ (Vector) RI-a O 370 and 390 Only A595 VMSDQ (Vector) RI-a O 370 and 390 Only A598 VCDQ (Vector) RI-a O 370 and 390 Only A599 VLDQ (Vector) RI-a O 370 and 390 Only A59A VLMDQ (Vector) RI-a O 370 and 390 Only A5A0 VAQ Add to Qualified reg. (Vector) RI-a A 370 and 390 Only A5A1 VSQ Subtract (Vector) RI-a A 370 and 390 Only A5A2 VMQ Multiply (Vector) RI-a A 370 and 390 Only A5A4 VNQ (Vector) RI-a O 370 and 390 Only A5A5 VOQ (Vector) RI-a O 370 and 390 Only A5A6 VXQ (Vector) RI-a O 370 and 390 Only A5A8 VCQ (Vector) RI-a O 370 and 390 Only A5A9 VLQ (Vector) RI-a O 370 and 390 Only A5AA VLMQ (Vector) RI-a O 370 and 390 Only A50 IIHH Insert Immediate High High RI-a D A51 IIHL Insert Immediate High Low RI-a D A52 IILH Insert Immediate Low High RI-a D A53 IILL Insert Immediate Low Low RI-a D A54 NIHH And Immediate High High RI-a A A55 NIHL And Immediate High Low RI-a A A56 NILH And Immediate Low High RI-a A A57 NILL And Immediate Low Low RI-a A A58 OIHH Or Immediate High High RI-a A A59 OIHL Or Immediate High Low RI-a A A5A OILH Or Immediate Low High RI-a A A5B OILL Or Immediate Low Low RI-a A A5C LLIHH Load Logical Immediate High High RI-a D A5D LLIHL Load Logical Immediate High Low RI-a D A5E LLILH Load Logical Immediate Low High RI-a D A5F LLILL Load Logical Immediate Low Low RI-a D A6-- Vector Instructions RRE O 370 and 390 Only A600 VMXSE (Vector) RRE O 370 and 390 Only A601 VMNSE (Vector) RRE O 370 and 390 Only A602 VMXAE (Vector) RRE O 370 and 390 Only A608 VLELE (Vector) RRE O 370 and 390 Only A609 VXELE (Vector) RRE O 370 and 390 Only A610 VMXDS (Vector) RRE O 370 and 390 Only A611 VMNSD (Vector) RRE O 370 and 390 Only A612 VMXAD (Vector) RRE O 370 and 390 Only A618 VLELD (Vector) RRE O 370 and 390 Only A619 VXELD (Vector) RRE O 370 and 390 Only A61A VSPSD (Vector) RRE O 370 and 390 Only A61B VZPSD (Vector) RRE O 370 and 390 Only A640 VTVM (Vector) RRE O 370 and 390 Only A641 VCVM (Vector) RRE O 370 and 390 Only A642 VCZVM (Vector) RRE O 370 and 390 Only A643 VCOVM (Vector) RRE O 370 and 390 Only A644 VXVC (Vector) RRE O 370 and 390 Only A645 VLVCU (Vector) RRE O 370 and 390 Only A646 VXVMM (Vector) RRE O 370 and 390 Only A648 VRRS (Vector) RRE O 370 and 390 Only A649 VRSVC (Vector) RRE O 370 and 390 Only A64A VRSV (Vector) RRE O 370 and 390 Only A680 VLVM (Vector) RRE O 370 and 390 Only A681 VLCVM (Vector) RRE O 370 and 390 Only A682 VSTVM (Vector) RRE O 370 and 390 Only A684 VNVM (Vector) RRE O 370 and 390 Only A685 VOVM (Vector) RRE O 370 and 390 Only A686 VXVM (Vector) RRE O 370 and 390 Only A6C0 VSRSV (Vector) RRE O 370 and 390 Only A6C1 VMRSV (Vector) RRE O 370 and 390 Only A6C2 VSRRS (Vector) RRE O 370 and 390 Only A6C3 VMRRS (Vector) RRE O 370 and 390 Only A6V4 VLVCA (Vector) RRE O 370 and 390 Only A6C5 VRCL (Vector) RRE O 370 and 390 Only A6C6 VSVMM (Vector) RRE O 370 and 390 Only A6C7 VLVXA (Vector) RRE O 370 and 390 Only A6C8 VSTVP (Vector) RRE O 370 and 390 Only A6CA VACSV Activity Count SaVe (Vector) RRE O 370 and 390 Only A6CB VACRS Activity Count ReStore (Vector) RRE O 370 and 390 Only A70 TMH Test under Mask High RI-a L A70 TMLH Test under Mask Low High RI-a L A71 TML Test under Mask Low RI-a L A71 TMLL Test under Mask Low Low RI-a L A72 TMHH Test under Mask High High RI-a L A73 TMHL Test under Mask High Low RI-a L A74 BRC Branch Relative on Condition RI-c B A74 JC Jump on Condition RI-c B A74-0 BRNOP Branch Relative No Operation RI-c B A74-0 JNOP Jump No Operation RI-c B A74-1 BRO Branch Relative on Overflow RI-c B A74-1 JO Jump on Overflow RI-c B A74-2 BRH Branch Relative on High RI-c B A74-2 JH Jump on High RI-c B A74-2 BRP Branch Relative on Plus RI-c B A74-2 JP Jump on Plus RI-c B A74-4 BRL Branch Relative on Low RI-c B A74-4 JL Jump on Low RI-c B A74-4 BRM Branch Relative on Minus RI-c B A74-4 JM Jump on Minus RI-c B A74-7 BRNE Branch Relative on Not Equal RI-c B A74-7 JNE Jump on Not Equal RI-c B A74-7 BRNZ Branch Relative on Not Zero RI-c B A74-7 JNZ Jump on Not Zero RI-c B A74-8 BRE Branch Relative on Equal RI-c B A74-8 JE Jump on Equal RI-c B A74-B BRNL Branch Relative on Not Low RI-c B A74-B JNL Jump on Not Low RI-c B A74-B BRNM Branch Relative on Not Minus RI-c B A74-B JNM Jump on Not Minus RI-c B A74-D BRNH Branch Relative on Not High RI-c B A74-D JNH Jump on Not High RI-c B A74-D BRNP Branch Relative on Not Plus RI-c B A74-D JNP Jump on Not Plus RI-c B A74-E BRNO Branch Relative on No Overflow RI-c B A74-E JNO Jump on No Overflow RI-c B A74-F BRU Branch Relative Unconditional RI-c B A74-F JU Jump Unconditional RI-c B A75 BRAS Branch Relative and Save RI-b B A76 BRCT Branch Relative on Count RI-b B A76 JCT Jump on Count RI-b B A77 BRCTG Branch Relative on Count 64 RI-b B A77 JCTG Jump on Count 64 RI-b B A78 LHI Load Halfword Immediate RI-a D A79 LGHI Load Halfword Immediate 64 RI-a D A7A AHI Add Halfword Immediate RI-a A A7B AGHI Add Halfword Immediate 64 RI-a A A7C MHI Multiply Halfword Immediate RI-a A A7D MGHI Multiply Halfword Immediate 64 RI-a A A7E CHI Compare Halfword Immediate RI-a L A7F CGHI Compare Halfword Immediate 64 RI-a L A8 MVCLE Move Long Extended RS D A9 CLCLE Compare Logical Long Extended RS L AC STNSM Store Then aNd System Mask SI P AD STOSM Store Then Or System Mask SI P AE SIGP Signal Processor RS P AF MC Monitor Call SI O B1 LRA Load Real Address RX P B200 CONCS 370 only Connect Channel Set S P B200 LBEAR Load BEAR S P B201 DISCS 370 only DISconnect Channel Set S P B201 STBEAR STore BEAR S P B202 STIDP Store CPU ID S P B204 SCK Set Clock S P B205 STCK Store Clock S D B206 SCKC Set Clock Comparator S P B207 STCKC Store Clock Comparator S P B208 SPT Set CPU Timer S P B209 STPT Store CPU Timer S P B20A SPKA Set PSW Key From Address S P B20B IPK Insert PSW Key S P B20D PTLB Purge TLB S P B210 SPX Set Prefix S P B211 STPX Store Prefix S P B212 STAP Store CPU Address S P B213 RRB Reset Reference Bit S P B214 SIE RI-a O 390 Only B218 PC Program Call S C B218 PCF Program Call Fast S C B219 SAC Set Address Space Control S C B21A CFC Compare and Form Codeword S L B21B DEP O B21C DCTP O B21D MAD Multiply and Add Long A B21E MUN O B21F STCAP O B220 SERVC O B221 IPTE Invalidate Page Table Entry RRF P B222 IPM Insert Program Mask RRE O B223 IVSK Insert Virtual Storage Key RRE P B224 IAC Insert Address Space Control RRE P B225 SSAR Set Secondary ASN RRE P B226 EPAR Extract Primary ASN RRE P B227 ESAR Extract Secondary ASN RRE P B228 PT Program Transfer RRE P B229 ISKE Insert Storage Key Extended RRE P B22A RRBE Reset Reference Bit Extended RRE P B22B SSKE Set Storage Key Extended RRE P B22C TB Test Block RRE P B22D DXR Divide Extended RRE D B22E PGIN Page In RRE P B22F PGOUT Page Out RRE P B230 CSCH Clear SubCHannel S P B231 HSCH Halt SubCHannel S P B232 MSCH Modify SubCHannel S P B233 SSCH Start SubCHannel S P B234 STSCH Store SubCHannel S P B235 TSCH Test SubCHannel S P B236 TPI Test Pending Interruption S P B237 SAL Set Address Limit S P B238 RSCH Resume SubCHannel S P B239 STCRW Store Channel Report Word S P B23A STCPS Store Channel Path Status S P B23B RCHP Reset Channel Path S P B23C SCHM Set Channel Monitor S P B23D STZP O B23E SZP O B23F TPZI O B240 BAKR Branch and Stack RRE D B241 CKSM Checksum RRE D B242 Add FRR RRE O B243 MADS O B244 SQDR Square Root Long RRE A B245 SQER Square Root Short RRE A B246 STURA STore Using Real Address RRE P B247 MSTA Modify Stacked state RRE C B248 PALB Purge ALB RRE P B249 EREG Extract Stacked Registers RRE D B24A ESTA Extract Stacked State RRE C B24B LURA Load Using Real Address RRE P B24C TAR Test Access RRE C B24D CPYA Copy Access RRE O B24E SAR Set Access RRE D B24F EAR Extract Access RRE D B250 CSP Compare and Swap and Purge RRE C B252 MSR Multiply Single RRE D B254 MVPG Move Page RRE P B255 MVST Move String RRE D B257 CUSE Compare Until Substring Equal RRE L B258 BSG Branch in Subspace Group RRE B B259 IESBE RRE O B25A BSA Branch and Set Authority RRE B B25B Asynchronus Page Facility RRE O B25C Asynchronus Page Facility RRE O B25D CLST Compare Logical String RRE L B25E SRST Search String RRE C B260 Coupling Facility RRE O B261 Coupling Facility RRE O B263 CMPSC Compression Call RRE O B264 Coupling Facility RRE O B266 Coupling Facility RRE O B267 Coupling Facility RRE O B269 Cryptographic Facility RRE O B26A Cryptographic Facility RRE O B26B Cryptographic Facility RRE O B26C Cryptographic Facility RRE O B26D Cryptographic Facility RRE O B26E Cryptographic Facility RRE O B26F Cryptographic Facility RRE O B272 Coupling Facility RRE O B276 XSCH Cancel SubCHannel S O B277 RP Resume Program S P B278 STCKE Store Clock Extended S D B279 SACF Set Address Space Control Fast S C B27A Coupling Facility RRE O B27B Coupling Facility RRE O B27C STCKF Store Clock Fast S O B27D STSI Store System Information S P B27E Coupling Facility RRE O B27F Coupling Facility RRE O B28F QPACI Query Processor Activity Counter Information S P B299 SRNM Set Rounding Mode S D B29C STFPC Store FPC S D B29D LFPC Load FPC S D B2A5 TRE Translate Extended RRE D B2A6 CU21 Convert UTF-16 to UTF-8 RRF-c D B2A6 CUUTF Convert Unicode to UTF-8 RRF-c D B2A7 CU12 Convert UTF-8 to UTF-16 RRF-c D B2A7 CUTFU Convert UTF-8 to Unicode RRF-c D B2AA Dequeue CAM RRE O B2AB Process CAM Queue RRE O B2AC Enqueue CAM RRE O B2B1 STFL Store Facility List S P B2B2 LPSWE Load PSW Extended S P B2B8 SRNMB Set Rounding Mode S D B2B9 SRNMT Set Decimal Rounding Mode S O B2BD LFAS Load FPC and Signal S O B2F6 Coupling Facility RRE O B2F8 TEND Transaction END S C B2FC TABORT Transaction ABORT S C B2FF TRAP4 Trap S C B300 LPEBR Load Positive Short RRE D B301 LNEBR Load Negative Short RRE D B302 LTEBR Load and Test Short RRE D B303 LCEBR Load Complement Short RRE D B304 LDEBR Load Lengthened Short/Long RRE D B305 LXDBR Load Lengthened Long/Extended RRE D B306 LDEBR Load Lengthened Short/Extended RRE D B307 MXDBR Multiply Long/Extended RRE A B308 KEBR Compare and Signal Short RRE L B309 CEBR Compare Short RRE L B30A AEBR Add Short RRE A B30B SEBR Subtract Short RRE A B30C MDEBR Multiply Short/Long RRE A B30D DEBR Divide Short RRE A B30E MAEBR Multiply and Add Short RRE A B30F MSEBR Multiply and Subtract Short RRE A B310 LPDBR Load Positive Long RRE D B311 LNDBR Load Negative Long RRE D B312 LTDBR Load and test Long RRE D B313 LCDBR Load Complement Long RRE D B314 SQEBR Square Root Short RRE A B315 SQDBR Square Root Long RRE A B316 SQXBR Square Root Extended RRE A B317 MEEBR Multiply Short RRE A B318 KDBR Compare and Signal Long RRE L B319 CDBR Compare Long RRE L B31A ADBR Add Long RRE A B31B SDBR Subtract Long RRE A B31C MDBR Multiply Long RRE A B31D DDBR Divide Long RRE A B31E MADBR Multiply and Add Long RRE A B31F MSDBR Multiply and Subtract Long RRE A B324 LDER Load Lengthened Short/Long RRE D B325 LXDR Load Lengthened Long/Extended RRE D B326 LXER Load Lengthened Short/Extended RRE D B32E MAER Multiply and Add Short RRF A B32F MSER Multiply and Subtract Short RRF A B336 SQXR Square Root Extended RRE A B337 MEER Multiply (Short*Short to Short) RRE A B338 MAYLR Multiply and Add Unnormalized (Long>Ext. Low) RRD A B339 MYLR Multiply Unnormalized (Long>Ext. Low) RRD A B33A MAYR Multiply and Add Unnormalized (Long>Extended) RRD A B33B MYR Multiply Unnormalized (Long>Extended) RRD A B33C MAYHR Multiply and Add Unnormalized (Long>Ext. High) RRD A B33D MYHR Multiply Unnormalized (Long>Ext. High) RRD A B33E MADR Multiply and Add Long RRF A B33F MSDR Multiply and Subtract Long RRF A B340 LPXBR Load Positive Extended RRE D B341 LNXBR Load Negative Extended RRE D B342 LTXBR Load and Test Extended RRE D B343 LCXBR Load Complement Extended RRE D B344 LEDBR Load Rounded Long/Short RRE D B344 LEDBRA Load Rounded Long/Short RRF-e D B345 LDXBR Load Rounded Extended/Long RRE D B345 LDXBRA Load Rounded Extended/Long RRF-e D B346 LEXBR Load Rounded Extended/Short RRE D B346 LEXBRA Load Rounded Extended/Short RRF-e D B347 FIXBR Load FP Integer Extended RRF-e D B348 KXBR Compare and Signal Extended RRE L B349 CXBR Compare Extended RRE L B34A AXBR Add Extended RRE A B34B SXBR Subtract Extended RRE A B34C MXBR Multiply Extended RRE A B34D DXBR Divide Extended RRE A B350 TBEDR Convert Short to Long RRF D B351 TBDR Convert Long RRF D B353 DIEBR Divide to Integer Short RRF A B357 FIEBR Load FP Integer Short RRF-e D B357 FIEBRA Load FP Integer Short RRF-e D B358 THDER Convert Short to Long RRE D B359 THDR Convert Long RRE D B35B DIDBR Divide to Integer Long RRF A B35F FIDBR Load FP Integer Long RRF-e D B35F FIDBRA Load FP Integer Long RRF-e D B360 LPXR Load Positive Extended RRE D B361 LNXR Load Negative Extended RRE D B362 LTXR Load and Test Extended RRE D B363 LCXR Load Complement Extended RRE D B365 LXR Load Extended RRE D B366 LEXR Load Rounded Extended/Short RRE D B367 FIXR Load FP Integer Extended RRF-e D B367 FIXRA Load FP Integer Extended RRF-e D B369 CXR Compare Extended RRE L B370 LPDFR Load Positive (Long) RRE D B371 LNDFR Load Negative (Long) RRE D B372 CPSDR Copy Sign (Long) RRF O B373 LCDFR Load Complement (Long) RRE D B374 LZER Load Zero (Short) RRE D B375 LZDR Load Zero (Long) RRE D B376 LZXR Load Zero (Extended) RRE D B377 FIER Load FP Integer (Short) RRE D B37F FIDR Load FP Integer (Long) RRE D B384 SFPC Set FPC RRE O B385 SFASR Set FPC and Signal RRE O B38C EFPC Extract FPC RRE O B390 CELBRA Convert from Logical (32/Short) RRF-e O B391 CDLBRA Convert from Logical (32/Long) RRF-e O B392 CXLBRA Convert from Logical (32/Extended) RRF-e O B394 CEFBR Convert from Fixed (32/Short) RRE O B394 CEFBRA Convert from Fixed (32/Short) RRF-e O B395 CDFBR Convert from Fixed (32/Long) RRE O B395 CDFBRA Convert from Fixed (32/Long) RRF-e O B396 CXFBR Convert from Fixed (32/Extended) RRE O B396 CXFBRA Convert from Fixed (32/Extended) RRF-e O B398 CFEBR Convert to Fixed (32/Short) RRF-e O B398 CFEBRA Convert to Fixed (32/Short) RRF-e O B399 CFDBR Convert to Fixed (32/Long) RRF-e O B399 CFDBRA Convert to Fixed (32/Long) RRF-e O B39A CFXBR Convert to Fixed (32/Extended) RRF-e O B39A CFXBRA Convert to Fixed (32/Extended) RRF-e O B39C CLFEBR Convert to Logical (32/Short) RRF-e O B39D CLFDBR Convert to Logical (32/Long) RRF-e O B39E CLFXBR Convert to Logical (32/Extended) RRF-e O B3A0 CELBRA Convert from Logical (64/Short) RRF-e O B3A1 CDLBRA Convert from Logical (64/Long) RRF-e O B3A2 CXLBRA Convert from Logical (64/Exteded) RRF-e O B3A4 CEGBR Convert from Fixed (64/Short) RRE O B3A4 CEGBRA Convert from Fixed (64/Short) RRF-e O B3A5 CDGBR Convert from Fixed (64/Long) RRE O B3A5 CDGBRA Convert from Fixed (64/Long) RRF-e O B3A6 CXGBR Convert from Fixed (64/Exteded) RRE O B3A6 CXGBRA Convert from Fixed (64/Exteded) RRF-e O B3A8 CGEBR Convert to Fixed (64/Short) RRF-e O B3A8 CGEBRA Convert to Fixed (64/Short) RRF-e O B3A9 CGDBR Convert to Fixed (64/Long) RRF-e O B3A9 CGDBRA Convert to Fixed (64/Long) RRF-e O B3AA CGXBR Convert to Fixed (64/Extended) RRF-e O B3AA CGXBRA Convert to Fixed (64/Extended) RRF-e O B3AC CLGEBR Convert to Logical (64/Short) RRF-e O B3AD CLGDBR Convert to Logical (64/Long) RRF-e O B3AE CLGXBR Convert to Logical (64/Extended) RRF-e O B3B4 CEFR Convert from Fixed (32/Short) RRE O B3B5 CDFR Convert from Fixed (32/Long) RRE O B3B6 CXFR Convert from Fixed (32/Extended) RRE O B3B8 CFER Convert to Fixed (Short/32) RRF O B3B9 CFDR Convert to Fixed (Long/32) RRF O B3BA CFXR Convert to Fixed (Extended/32) RRF O B3C1 LDGR Load FPR from GPR (Long) RXY D B3C4 CEGR Convert from Fixed (64/Short) RRE O B3C5 CDGR Convert from Fixed (64/Long) RRE O B3C6 CXGR Convert from Fixed (64/Extended) RRE O B3C8 CGER Convert to Fixed (Short/64) RRF O B3C9 CGDR Convert to Fixed (Long/64) RRF O B3CA CGXR Convert to Fixed (Extended/64) RRF O B3CD LGDR Load GPR from FPR (Long) RXY D B3D0 MDTR Multiply (Long) RRR A B3D0 MDTRA Multiply (Long) RRF-a A B3D1 DDTR Divide (Long) RRF-a A B3D2 ADTR Add (Long) RRF-a A B3D2 ADTRA Add (Long) RRF-a A B3D3 SDTR Subtract (Long) RRF-a A B3D3 SDTRA Subtract (Long) RRF-a A B3D4 LDETR Load Lengthened (Short/Long) RRF-d D B3D5 LEDTR Load Rounded (Long/Short) RRF-e D B3D6 LTDTR Load and Test (Long) RRE D B3D7 FIDTR Load Floating-Point Integer (Long) RRF-e D B3D8 MXTR Multiply (Extended) RRF-a A B3D8 MXTRA Multiply (Extended) RRF-a A B3D9 DXTR Divide (Extended) RRF-a A B3DA AXTR Add (Extended) RRF-a A B3DA AXTRA Add (Extended) RRF-a A B3DB SXTR Subtract (Extended) RRF-a A B3DB SXTRA Subtract (Extended) RRF-a A B3DC LXDTR Load Lengthened (Long/Extended) RRF D B3DD LDXTR Load Rounded (Extended/Long) RRF D B3DE LTXTR Load and Test (Extended) RRE D B3DF FIXTR Load Floating-Point Integer (Extended) RRF D B3E0 KDTR Compare and Signal (Long) RRE L B3E1 CGDTR Convert to Fixed (Long/64) RRF-e O B3E1 CGDTRA Convert to Fixed (Long/64) RRF-e O B3E2 CUDTR Convert to 64b U.Packed (Long) RRF O B3E3 CSDTR Convert to 64b S.Packed (Long) RRF O B3E4 CDTR Compare (Long) RRE L B3E5 EEDTR Extract Biased Exponent (Long) RRE O B3E7 ESDTR Extract Significance (Long) RRE O B3E8 KXTR Compare and Signal (Extended) RRE L B3E9 CGXTR Convert to Fixed (Extended/64) RRF-e O B3E9 CGXTRA Convert to Fixed (Extended/64) RRF-e O B3EA CUXTR Convert to 128b U.Packed (Extended) RRF O B3EB CSXTR Convert to 128b S.Packed (Extended) RRF O B3EC CXTR Compare (Extended) RRE L B3ED EEXTR Extract Biased Exponent (Extended) RRE O B3EF ESXTR Extract Significance (Extended) RRE O B3F1 CDGTR Convert from Fixed (64/Long) RRE O B3F1 CDGTRA Convert from Fixed (64/Long) RRE O B3F2 CUSTR Convert from 64b U.Packed (Long) RRE O B3F3 CDSTR Convert from 64b S.Packed (Long) RRE O B3F4 CEDTR Compare Biased Exponent (Long) RRE L B3F5 QADTR Quantize (Long) RRF-b O B3F6 IEDTR Insert Biased Exponent (Long) RRF-b O B3F7 RRDTR Reround (Long) RRF-b O B3F9 CXGTR Convert from Fixed (64/Extended) RRE O B3F9 CXGTRA Convert from Fixed (64/Extended) RRE O B3FA CXUTR Convert from 128b U.Packed (Extended) RRE O B3FB CXSTR Convert from 128b S.Packed (Extended) RRE O B3FC CEXTR Compare Biased Exponent (Extended) RRE L B3FD QAXTR Quantize (Extended) RRF-b O B3FE IEXTR Insert Biased Exponent (Extended) RRF-b O B3FF RRXTR Reround (Extended) RRF-b O B6 STCTL Store ConTroL RS P B7 LCTL Load ConTroL RS P B8 LMC Load Multiple Control RS P B900 LPGR Load Positive Register (64 bit) D B901 LNGR Load Negative Register (64 bit) D B902 LTGR Load and Test Register (64 bit) D B903 LCGR Load and Complement Register (64 bit) RRE D B904 LGR Load Register (64 bit) RRE D B905 LURAG Load Using Real Address (64 bit) RRE P B906 LGBR Load Byte (8/64) RRE D B908 AGR Add (64) RRE A B909 SGR Subtract (64) RRE A B90A ALGR Add Logical (64) RRE A B90B SLGR Subtract Logical (64) RRE A B90C MSGR Multiply Single (64) RRE A B90D DSGR Divide Single (64) RRE A B90E EREGG Extract Stacked Registers (64) RRE D B90F LRVGR Load Reversed (64) RRE D B910 LPGFR Load Positive (32/64) RRE D B911 LNGFR Load Negative (32/64) RRE D B912 LTGFR Load And Test (32/64) RRE D B913 LCGFR Load Complement (32/64) RRE D B914 LGFR Load (32/64) RRE D B916 LLGFR Load Logical (32/64) RRE D B917 LLGTR Load Logical Thirty One Bits (31/64) RRE D B918 AGFR Add (32/64) RRE A B919 SGFR Subtract (32/64) RRE A B91A ALGFR Add Logical (32/64) RRE A B91B SLGFR Subtract Logical (32/64) RRE A B91C MSGFR Multiply Single (32/64) RRE A B91D DSGFR Divide Single (32/64) RRE A B91F LRVR Load Reversed (32) RRE D B920 CGR Compare (64) RRE L B921 CLGR Compare Logical (64) RRE L B925 STURG Store Using Real Address RRE P B926 LBR Load Byte (8/32) RRE D B927 LHR Load Halfword (32<16) RRE D B928 PCKMO Perform Cryptographic Key Mgmt Operations RRE P B929 KMA cipher Message with Authentication RRF-b O B92A KMF cipher Message with cipher Feedback RRE O B92B KMO cipher Message with Output feedback RRE O B92C PCC Perform Cryptographic Computation RRE O B92D KMCTR cipher Message with CounTeR RRF-b O B92E KM cipher Message RRE O B92F KMC cipher Message with Chaining RRE O B930 CGFR Compare (32/64) RRE L B931 CLGFR Compare Logical (32/64) RRE L B938 SORTL Sort Lists RRE O B939 DFLTCC deflate conversion call RRF-a O B93A KDSA compute digital signature authentication RRE O B93B NNPA Neural Network Processing Assist RRE O B93C PRNO perform random number operation RRE O B93E KIMD compute intermediate message digest RRE O B93F KLMD compute last message digest RRE O B941 CFDTR Convert to fixed (Long Dfp to 32) RRF-e O B942 CLGDTR Convert to logical (Long Dfp to 64) RRF-e O B943 CLFDTR Convert to logical (Long Dfp to 32) RRF-e O B946 BCTGR Branch on CounT (64) RRE B B949 CFXTR Convert to Fixed (eXtended Dfp to 32) RRF-e O B94A CLGXTR Convert to Logical (eXtended Dfp to 64) RRF-e O B94B CLFXTR Convert to Logical (eXtended Dfp to 32) RRF-e O B951 CDFTR Convert from fixed (32 to Long Dfp) RRE O B952 CDLGTR Convert from Logical (64 to Long Dfp) RRF-e O B953 CDLFTR Convert from Logical (32 to Long Dfp) RRF-e O B959 CXFTR Convert from Fixed (32 to eXtended Dfp) RRE O B95A CXLGTR Convert from Logical (64 to eXtended Dfp) RRF-e O B95B CXLFTR Convert from Logical (32 to eXtended Dfp) RRF-e O B960 CGRT Compare and Trap (64) RRF-c L B960-2 CRTH Compare and Trap on High (32) RRF-c L B960-4 CRTL Compare and Trap on Low (32) RRF-c L B960-7 CRTE Compare and Trap on Equal(32) RRF-c L B960-8 CRTNE Compare and Trap on Not Equal (32) RRF-c L B960-A CRTNL Compare and Trap on Not Low (32) RRF-c L B960-C CRTNH Compare and Trap on Not High (32) RRF-c L B961 CLGRT Compare Logical and Trap (64) RRF L B964 NNGRK Nand (64) RRF-a O B965 OCGRK Or with Complement (64) RRF-a O B966 NOGRK Nor (64) RRF-a O B967 NXGRK Not eXclusive or (64) RRF-a O B972 CRT Compare and Trap (32) RRF-c L B972-2 CRTH Compare and Trap on High (32) RRF-c L B972-4 CRTL Compare and Trap on Low (32) RRF-c L B972-7 CRTE Compare and Trap on Equal(32) RRF-c L B972-8 CRTNE Compare and Trap on Not Equal (32) RRF-c L B972-A CRTNL Compare and Trap on Not Low (32) RRF-c L B972-C CRTNH Compare and Trap on Not High (32) RRF-c L B973 CLRT Compare Logical and Trap (32) RRF-c L B973-2 CLRTH Compare Logical and Trap on High (32) RRF-c L B973-4 CLRTL Compare Logical and Trap on Low (32) RRF-c L B973-7 CLRTE Compare Logical and Trap on Equal(32) RRF-c L B973-8 CLRTNE Compare Logical and Trap on Not Equal (32) RRF-c L B973-A CLRTNL Compare Logical and Trap on Not Low (32) RRF-c L B973-C CLRTNH Compare Logical and Trap on Not High (32) RRF-c L B974 NNRK Nand (32) RRF-a O B975 OCRK Or with Complement (32) RRF-a O B976 NORK Nor (32) RRF-a O B977 NXRK Not eXclusive or (32) RRF-a O B980 NGR aNd (64) RRE A B981 OGR Or (64) RRE A B982 XGR eXclusive or (64) RRE A B984 LLGCR Load Logical Character (8/64) RRE D B985 LLGHR Load Logical Halfword (16/64) RRE D B986 MLGR Multiply Logical (64/128) RRE A B987 DLGR Divide Logical (128/64) RRE A B988 ALCGR Add Logical with Carry (64) RRE A B989 SLBGR Subtract Logical with Borrow (64) RRE A B98B RDP Reset DAT Protection RRF-b P B98D EPSW Extract PSW RRE O B98E IDTE Invalidate DAT Table Entry RRF-b P B98F CRDTE Compare and Replace DAT Table Entry RRF-b P B990 TRTT Translate Two To Two RRF-c D B991 TRTO Translate Two To One RRF-c D B992 TROT Translate One To Two RRF-c D B993 TROO Translate One To One RRF-c D B994 LLCR Load Logical Character (8/32) RRE D B995 LLHR Load Logical Halfword (16/32) RRE D B996 MLR Multiply Logical (32/64) RRE A B997 DLR Divide Logical (64/32) RRE A B998 ALCR Add Logical with Carry RRE A B999 SLBR Subtract Logical with Borrow RRE A B99A EPAIR Extract Primary ASN and Instance RRE P B99B ESAIR Extract Secondary ASN and Instance RRE P B99D ESEA Extract and Set Extended Authority RRE P B99E PTI Program Transfer with Instance RRE P B99F SSAIR Set Secondary ASN and Instance RRE P B9A1 TPEI Test Pending External Interruption RRE P B9A2 PTF Perform Topology Function RRE P B9AA LPTEA Load Page Table Entry Address RRF-b P B9AC IRBM Insert Reference Bits Multiple RRE C B9AE RRBM Reset Reference Bits Multiple RRE P B9AF PFMF Perform Frame Management Function RRE P B9B0 CU14 Convert UTF-8 to UTF-32 RRF-c D B9B1 CU24 Convert UTF-16 to UTF-32 RRF-c D B9B2 CU41 Convert UTF-32 to UTF-8 RRE D B9B3 CU42 Convert UTF-32 to UTF-16 RRE D B9BD TRTE TRanslate and Test Reverse Extended RRF-c D B9BE SRSTU Search String Unicode RRE L B9BF TRTE TRanslate and Test Extended RRF-c D B9C0 SELFHR SELect High (32) RRF-a O B9C8 AHHHR Add High (32) RRF-a A B9C9 SHHHR Subtract High (32) RRF-a A B9CA ALHHHR Add Logical High (32) RRF-a A B9CB SLHHHR Subtract Logical High (32) RRF-a A B9CD CHHR Compare High (32) RRE L B9CF CLHHR Compare Logical High (32) RRE L B9D8 AHHLR Add High (32) RRF-a A B9D9 SHHLR Subtract High (32) RRF-a A B9DA ALHHLR Add Logical High (32) RRF-a A B9DB SLHHLR Subtract Logical High (32) RRF-a A B9DD CHLR Compare High (32) RRE L B9DF CLHLR Compare Logical High (32) RRE L B9E0 LOCFHR Load High on Condition (32) RRF-c O B9E1 POPCNT POPulation CouNT RRF-c O B9E2 LOCGR Load on Condition (64) RRF-c O B9E3 SELGR SELect (64) RRF-a L B9E4 NGRK aNd (64) RRF-a A B9E5 NCGRK aNd with Complement (64) RRF-a A B9E6 OGRK OR (64) RRF-a A B9E7 XGRK eXclusive or (64) RRF-a A B9E8 AGRK Add (64) RRF-a A B9E9 SGRK Subtract (64) RRF-a A B9EA ALGRK Add Logical (64) RRF-a A B9EB SLGRK Subtract Logical (64) RRF-a A B9EC MGRK Multiply (128<64) RRF-a A B9ED MSGRKC Multiply Single (64) RRF-a A B9F0 SELR SELect (32) RRF-a L B9F2 LOCR Load On Condition (32) RRF-c D B9F4 NRK aNd (32) RRF-a A B9F5 NCRK aNd with Complement (32) RRF-a A B9F6 ORK OR (32) RRF-a A B9F7 XRK eXclusive or (32) RRF-a A B9F8 ARK Add (32) RRF-a A B9F9 SRK Subtract (32) RRF-a A B9FA ALRK Add Logical (32) RRF-a A B9FB SLRK Subtract Logical (32) RRF-a A B9FD MSRKC Multiply Single (32) RRF-a A BA CS Compare and Swap RS L BB CDS Compare Double and Swap RS L BD CLM Compare Logical Chars. under Mask RS L BE STCM Store Characters under Mask RS D BF ICM Insert Characters under Mask RS D C00 LARL Load Address Relative Long RIL D C01 LGFI Load Immediate (32/64) RIL D C04 BRCL Branch Relative on Condition Long RIL B C04 JCL Jump on Condition Long RIL B C04-0 BRUL No Operation RIL B C04-0 JLNOP No Operation RIL B C04-1 BROL Branch Relative Long on Overflow RIL B C04-1 JLO Jump Long on Overflow RIL B C04-2 BRHL Branch Relative Long on High RIL B C04-2 JLH Jump Long on High RIL B C04-2 BRPL Branch Relative Long on Plus RIL B C04-2 JLP Jump Long on Plus RIL B C04-4 BRLL Branch Relative Long on Low RIL B C04-4 JLL Jump Long on Low RIL B C04-4 BRML Branch Relative Long on Minus RIL B C04-4 JLM Jump Long on Minus RIL B C04-7 BRNEL Branch Relative Long on Not Equal RIL B C04-7 JLNE Jump Long on Not Equal RIL B C04-7 BRNZL Branch Relative Long on Not Zero RIL B C04-7 JLNZ Jump Long on Not Zero RIL B C04-8 BREL Branch Relative Long on Equal RIL B C04-8 JLEQ Jump Long on Equal RIL B C04-8 BRZL Branch Relative Long on Zero RIL B C04-8 JLZ Jump Long on Zero RIL B C04-B BRLL Branch Relative Long on Not Low RIL B C04-B JLL Jump Long on Not Low RIL B C04-B BRNML Branch Relative Long on Not Minus RIL B C04-B JLNM Jump Long on Not Minus RIL B C04-D BRNHL Branch Relative Long on Not High RIL B C04-D JLNH Jump Long on Not High RIL B C04-D BRNPL Branch Relative Long on Not Plus RIL B C04-D JLNP Jump Long on Not Plus RIL B C04-E BRNOL Branch Relative Long on Not Overflow RIL B C04-E JLNO Jump Long on Not Overflow RIL B C04-F BRUL Unconditional Branch Relative Long RIL B C04-F JLU Unconditional Jump Long RIL B C05 BRASL Branch Relative and Save Long RIL B C06 XIHF eXclusive Or Immediate (high) RIL A C07 XILF eXclusive Or Immediate (low) RIL A C08 IIHF Insert Immediate (high) RIL D C09 IILF Insert Immediate (low) RIL D C0A NIHF aNd Immediate (high) RIL A C0B NILF aNd Immediate (low) RIL A C0C OIHF Or Immediate (high) RIL A C0D OILF Or Immediate (low) RIL A C0E LLIHF Load Logical Immediate (high) RIL D C0F LLILF Load Logical Immediate (low) RIL D C20 MSGFI Multiply Single Immediate (32/64) RIL A C21 MSFI Multiply Single Immediate (32) RIL A C24 SLGFI Subtract Logical Immediate (32/64) RIL A C25 SLFI Subtract Logical Immediate (32) RIL A C28 AGFI Add Immediate (32/64) RIL A C29 AFI Add Immediate (32) RIL A C2A ALGFI Add Logical Immediate (32/64) RIL A C2B ALFI Add Logical Immediate (32) RIL A C2C CGFI Compare Immediate (32/64) RIL L C2D CFI Compare Immediate (32) RIL L C2E CLGFI Compare Logical Immediate (32/64) RIL L C2F CLFI Compare Logical Immediate (32) RIL L C42 LLHRL Load Logical Halfword Relative Long (16/32) RIL D C44 LGHRL Load Halfword Relative Long (16/64) RIL D C45 LHRL Load Halfword Relative Long (16/32) RIL D C46 LLGHRL Load Logical Halfword Relative Long (16/64) RIL D C47 STHRL STore Halfword Relative Long RIL D C48 LGRL Load Relative Long (64) RIL D C4B STGRL STore Relative Long (64) RIL D C4C LGFRL Load Relative Long (32/64) RIL D C4D LRL Load Relative Long (32) RIL D C4E LLGFRL Load Logical Relative Long (32/64) RIL D C4F STRL Store Relative Long (32) RIL D C60 EXRL Execute Relative Long RIL C C62 PFDRL Prefetch Data Relative Long RIL D C64 CGHRL Compare Halfword Relative Long (16/64) RIL L C65 CHRL Compare Halfword Relative Long (16/32) RIL L C66 CLGHRL Compare Logical Relative Long (16/64) RIL L C67 CLHRL Compare Logical Relative Long (16/32) RIL L C68 CGRL Compare Relative Long (64) RIL L C6A CLGRL Compare Logical Relative Long (64) RIL L C6C CGFRL Compare Logical Relative Long (32/64) RIL L C6D CRL Compare Relative Long (32) RIL L C6E CLGFRL Compare Logical Relative Long (32/64) RIL L C6F CLRL Compare Logical Relative Long (32) RIL L C80 MVCOS MoVe Characters with Optional Specifications SSF C C61 ECTG Extract Cpu Time SSF O C62 CSST Compare and Swap and STore SSF L C7 BPP Branch Prediction Preload SMI B C84 LPD Load Pair Disjoint (32) SSF D C85 LPDG Load Pair Disjoint (64) SSF D CC6 BRCTH Branch Relative on CounT High (32) RIL-b B CC8 AIH Add Immediate High (32) RIL-a A CCA ALSIH Add Logical with Signed Immediate High (32) RIL-a A CCB ALSIHN Add Logical with Signed Immediate High (32) RIL-a O CCD CIH Compare Immediate High (32) RIL-a L CCF CLIH Compare Logical Immediate High (32) RIL-a L D0 TRTR TRanslate and Test Reverse SS-a D D1 MVN MoVe Numeric SS-a D D2 MVC MoVe Character SS-a D D3 MVZ MoVe Zone SS-a D D4 NC aNd Character SS-a D D5 CLC Compare Logical Character SS-a L D6 OC Or Character SS-a D D7 XC eXclusive-or Character SS-a D D9 MVCK Move with Key SS-d C DA MVCP Move to Primary SS-d C DB MVCS Move to Secondary SS-d C DC TR TRanslate SS-a D DD TRT TRanslate and Test SS-a D DE ED EDit SS-a D DF EDMK EDit and MarK SS-a D E1 PKU PacK (Unicode) SS-f D E2 UNPKU UNPacK (Unicode) SS-a D E302 LTG Load and Test (64) RXY-a D E303 LRAG Load Real Address (64) RXY-a O E304 LG Load (64) RXY-a D E306 CVBY ConVert to Binary (32) RXY-a D E308 AG Add (64) RXY-a A E309 SG Subtract (64) RXY-a A E30A ALG Add Logical (64) RXY-a A E30B SLG Subtract Logical (64) RXY-a A E30C MSG Multiply single (64) RXY-a A E30D DSG Divide single (64) RXY-a A E30E CVBG ConVert to Binary (64) RXY-a D E30F LRVG Load ReVersed (64) RXY-a D E312 LT Load and Test (32) RXY-a D E313 LRAY Load Real Address (32) RXY-a O E314 LGF Load Fullword (32/64) RXY-a D E315 LGH Load Halfword (64) RXY-a D E316 LLGF Load Logical (32/64) RXY-a D E317 LLGT Load Logical Thirty One Bits RXY-a D E318 AGF Add (32/64) RXY-a A E319 SGF Subtract (32/64) RXY-a A E31A ALGF Add Logical (32/64) RXY-a A E31B SLGF Subtract Logical (32/64) RXY-a A E31C MSGF Multiply Single (32/64) RXY-a A E31D DSGF Divide Single (32/64) RXY-a A E31E LRV Load Reversed (32) RXY-a D E31F LRVH Load Reversed (16) RXY-a D E320 CG Compare (64) RXY-a L E321 CLG Compare Logical (64) RXY-a L E324 STG Store (64) RXY-a D E325 NTSTG NonTransactional STore (64) RXY-a D E326 CVDY Convert to Decimal (32) RXY-a D E32A LZRG Load and Zero Rightmost Byte (64) RXY-a D E32E CVDG Convert to Decimal (64) RXY-a D E32F STRVG SToRe ReVersed (64) RXY-a D E330 CGF Compare Fullword (32/64) RXY-a L E331 CLGF Compare Logical (32/64) RXY-a L E332 LTGF Load and Test (32/64) RXY-a L E334 CGH Compare Halfword (16/64) RXY-a L E336 PFD PreFetch Data RXY-b D E338 AGH Add Halfword (64<16) RXY-a O E339 SGH Subtract Halfword (64<16) RXY-a O E33A LLZRGF Load Logical and Zero Rightmost Byte (64<32) RXY-a O E33B LZRF Load and Zero Rightmost Byte (32) RXY-a O E33C MGH Multiply Halfword (64<16) RXY-a O E33E STRV STore ReVersed (32) RXY-a D E33F STRVH STore ReVersed (16) RXY-a D E346 BCTG Branch on CounT (64) RXY-a B E347 BIC Branch Indirect on Condition RXY-b O E347-1 BIO Branch Indirect on Overflow RXY-b O E347-2 BIP Branch Indirect on Plus RXY-b O E347-2 BIH Branch Indirect on High RXY-b O E347-4 BIM Branch Indirect on Minus RXY-b O E347-4 BIL Branch Indirect on Low RXY-b O E347-7 BINZ Branch Indirect on Not Zero RXY-b O E347-7 BINE Branch Indirect on Not Equal RXY-b O E347-8 BIZ Branch Indirect on Zero RXY-b O E347-8 BIE Branch Indirect on Equal RXY-b O E347-B BINM Branch Indirect on Not Minus RXY-b O E347-B BINL Branch Indirect on Not Low RXY-b O E347-D BINP Branch Indirect on Not Plus RXY-b O E347-D BINH Branch Indirect on Not High RXY-b O E347-E BINO Branch Indirect on No Overflow RXY-b O E347-F BI Branch Indirect RXY-b O E348 LLGFSG Load Logical and Shift Guarded (64<32) RXY-a O E349 STGSC STore Guarded Storage Controls RXY-a O E34C LGG Load Guarded (64) RXY-a O E34D LGSC Load Guarded Storage Controls RXY-a O E350 STY Store (32) RXY-a D E351 MSY Multiply Single (32) RXY-a A E353 MSC Multiply Single (32) RXY-a O E354 NY aNd (32) RXY-a A E355 CLY Compare Logical (32) RXY-a L E356 OY Or (32) RXY-a A E357 XY eXclusive or (32) RXY-a A E358 LY Load (32) RXY-a D E359 CY Compare (32) RXY-a L E35A AY Add (32) RXY-a A E35B SY Subtract (32) RXY-a A E35C MFY Multiply (32/64) RXY-a A E35E ALY Add Logical (32) RXY-a A E35F SLY Subtract Logical (32) RXY-a A E370 STHY STore Halfword RXY-a D E371 LAY Load Address RXY-a D E372 STCY STore Character RXY-a D E373 ICY Insert Character RXY-a D E375 LAEY Load Address Extended RXY-a D E376 LB Load Byte (8/32) RXY-a D E377 LGB Load Byte (8/64) RXY-a D E378 LHY Load Halfword (32) RXY-a D E379 CHY Compare Halfword (16/32) RXY-a L E37A AHY Add Halfword RXY-a A E37B SHY Subtract Halfword RXY-a A E37C MHY Multiply Halfword (32) RXY-a A E380 NG aNd (64) RXY-a A E381 OG Or (64) RXY-a A E382 XG eXclusive or (64 bit) RXY-a A E383 MSGC Multiply Single (64) RXY-a O E384 MG Multiply (128<64) RXY-a O E385 LGAT Load and Trap (64) RXY-a O E386 MLG Multiply Logical (64/128) RXY-a A E387 DLG Divide Logical (128/64) RXY-a A E388 ALCG Add Logical with Carry (64) RXY-a A E389 SLBG Subtract Logical with Borrow (64) RXY-a A E38E STPQ STore Pair to Quadword RXY-a D E38F LPQ Load Pair from Quadword RXY-a D E390 LLGC Load Logical Character (8/64) RXY-a D E391 LLGH Load Logical Halfword (16/64) RXY-a D E394 LLC Load Logical Character (32) RXY-a D E395 LLH Load Logical Halfword (16/32) RXY-a D E396 ML Multiply Logical (32/64) RXY-a A E397 DL Divide Logical (64/32) RXY-a A E398 ALC Add Logical with Carry (32) RXY-a A E399 SLB Subtract Logical with Borrow (32) RXY-a A E39C LLGTAT Load Logical Thirty one bits and Trap (64<31) RXY-a O E39D LLGFAT Load Logical and Trap (64<32) RXY-a O E39F LAT Load and Trap (32<32) RXY-a O E3C0 LBH Load BYTE High (32<8) RXY-a O E3C2 LLCH Load Logical Character High (32<8) RXY-a O E3C3 STCH STore Character High (8) RXY-a O E3C4 LHH Load Halfword High (32<16) RXY-a O E3C6 LLHH Load Logical Halfword High (32<16) RXY-a O E3C7 STHH STore Halfword High (16) RXY-a O E3C8 LFHAT Load High and Trap (32<32) RXY-a O E3CA LFH Load High (32) RXY-a O E3CB STFH STore High (32) RXY-a O E3CD CHF Compare High (32) RXY-a L E3CF CLHF Compare Logical High (32) RXY-a L E4-- Vector Instructions RRE O 370 and 390 Only E400 VLI Vector Load Indirect RRE D 370 and 390 Only E401 VSTI Vector STore Indirect RRE D 370 and 390 Only E410 VLID Vector Load Indirect Double RRE D 370 and 390 Only E401 VSTID Vector Store Indirect Double RRE D 370 and 390 Only E424 VSRL Vector Shift Right single Logical RRE S 370 and 390 Only E425 VSLL Vector Shift Left single Logical RRE S 370 and 390 Only E428 VLBIX Vector Load Bit IndeX RRE D 370 and 390 Only E500 LASP Load Address Space Parameters SSE P E501 TPROT Test PROTection SSE P E502 Fix Page SS O MVS Assist E502 STRAG STore Real Address Grande SSE P E503 SVC Assist O MVS Assist E504 Obtain Local Lock O MVS Assist E505 Release Local Lock O MVS Assist E506 Obtain CMS Lock O MVS Assist E507 Release CMS Lock O MVS Assist E508 Trace SVC Interruption O MVS Assist E509 Trace Program Interruption O MVS Assist E50A Trace Initial SRB Dispach O MVS Assist E50A MVCRL MOVE Right to Left SSE D E50B Trace I/O Interruption O MVS Assist E50C Trace Task Dispach O MVS Assist E50D Trace SVC Return O MVS Assist E50E MVCSK Move with Source Key SSE C E50F MVCDK Move with Destination Key SSE C E518 DPFET Divide Packed Fetch O E544 MVHHI Move Halfword from Halfword Immediate SIL O E548 MVGHI Move Grande from Halfword Immediate SIL O E54C MVHI Move fullword from Halfword Immediate SIL O E554 CHHSI Compare Halfword with Halfword Signed Imm. SIL L E555 CLHHSI Comp. Log. Halfword w/Halfword Signed Imm. SIL L E558 CGHSI Comp. Grande w/Halfword Signed Imm. SIL L E559 CLGHSI Compare Log. Grande w/Halfword Imm. SIL L E55C CHSI Compare Halfword Signed Imm. SIL L E55D CLFHSI Compare Log. Fullword w/Halfword Signed Imm. SIL L E560 TBEGIN Transaction BEGIN SIL C E561 TBEGINC Transaction BEGIN Constrained SIL C E600 Get Free Storage Space O VM Assist E601 Return Free Storage Space O VM Assist E601 VLEBRH Vector Load Byte Reversed Element (16) VRX D E602 Lock Page O VM Assist E602 VLEBRG Vector Load Byte Reversed Element (64) VRX D E603 Unlock Page O VM Assist E603 VLEBRF Vector Load Byte Reversed Element (32) VRX D E604 Decode Subsequent CCW Commands O VM Assist E604 VLLEBRZ Vector Load Byte Reversed Element and Zero VRX D E605 Free CCW Storage O VM Assist E605 VLBRREP Vector Load Byte Reversed Element and REPlicate VRX D E606 Locate Virtual I/O Control Blocks O VM Assist E606 VLBR Vector Load Byte Reversed Elements VRX D E607 Dispatch a Block or Virtual Machine O VM Assist E607 VLER Vector Load Elements Reversed VRX D E608 Test Page Status O VM Assist E609 Test Page Status and Lock O VM Assist E609 VSTEBRH Vector STore Byte Reversed Element (16) VRX D E60A Invalidate Segment Table O VM Assist E60A VSTEBRG Vector STore Byte Reversed Element (64) VRX D E60B Invalidate Page Table O VM Assist E60B VSTEBRF Vector STore Byte Reversed Element (32) VRX D E60C Decode First CCW Command O VM Assist E60D Main Entry to Dispatcher O VM Assist E60E Locate Real I/O Control Blocks O VM Assist E60E VSTBR Vector STore Byte Reversed Elements VRX D E60F Common CCW Command Processing O VM Assist E60F VSTER Vector STore Elements Reversed VRX D E610 Untranslate CCW O VM Assist E611 Dispatch a Block or Virtual Machine O VM Assist E612 Store ECPS:VM/370 Identification O VM Assist E613 Locate Changed Shared Page O VM Assist E614 Get Free Storage Space (FRETX) O VM Assist E615 Return Free Storage Space (FRETX) O VM Assist E616 Preferred Machine Assist O VM Assist E634 VPKZ Vector PacK Zoned VSI D E635 VLRL Vector Load Rightmost with Length VSI D E637 VLRLR Vector Load Rightmost with Length VRS-d D E63C VUPKZ Vector UnPack ZONED VSI D E63D VSTRL Vector STore Rightmost with Length VSI D E63F VSTRLR Vector STore Rightmost with Length VRS-d D E649 VLIP Vector Load Immediate Decimal VRI-h D E650 VCVB Vector Convert to Binary VRR-i A E651 VCLZDP Vector Count Leading Zero Digits VRR-k A E652 VCVBG Vector Convert to Binary VRR-i A E654 VUPKZH Vector Unpack Zoned High VRR-k A E655 VCNF Vector FP Convert to NNP VRR-a A E656 VCLFNH Vector FP Convert and Lengthen from NNP High VRR-a A E658 VCVD Vector Convert to Decimal VRI-i A E659 VSRP Vector Shift and Round Decimal VRI-g S E65A VCVDG Vector Convert to Decimal VRI-i A E65B VPSOP Vector Perform Sign OPperation Decimal VRI-g A E65C VUPKZL Vector Unpack Zoned High VRR-k A E65D VCFN Vector FP Convert from NNP VRR-a A E65E VCLFNL Vector FP Convert and Lengthen from NNP Low VRR-a A E65F VTP Vector Test Decimal VRR-g L E670 VSP Vector Pack Zoned Register VRI-f A E671 VAP Vector Add Decimal VRI-f A E672 VSRPR Vector Shift and Round Decimal Register VRI-f A E673 VSP Vector Subtract Decimal VRI-f A E674 VSCHP Vector Scale and Convert to HFP VRR-b A E675 VCRNF Vector FP Convert and Round to NNP VRR-c A E677 VCP Vector Compare Decimal VRR-h L E678 VMP Vector Multiply Decimal VRI-f A E679 VMSP Vector Multiply and Shift Decimal VRI-f A E67A VDP Vector Divide Decimal VRI-f A E67B VRP Vector Remainder Decimal VRI-f A E67C VSCSHP Decimal Scale and Convert and Split to HFP VRR-b A E67D VCSPH Vector Convert HFP to Scaled Decimal VRR-j A E67E VSDP Vector Shift and Divide Decimal VRI-f A E700 VLEB Vector Load Element (8) VRX D E701 VLEH Vector Load Element (16) VRX D E702 SVC Handler without Trace O VS1 Assist E702 VLEG Vector Load Element (64) VRX D E703 SVC Handler with Trace O VS1 Assist E703 VLEF Vector Load Element (32) VRX D E704 Resume Page Measurement O VS1 Assist E704 VLLEZ Vector Load Logical Element and Zero VRX D E705 Resume Short Term Unfix O VS1 Assist E705 VLREP Vector Load and Replicate VRX D E706 VL Vector Load VRX D E707 Dispatcher O VS1 Assist E707 VLBB Vector Load to Block Boundary VRX D E708 SIO Trace O VS1 Assist E708 VSTEB Vector STore Element (8) VRX D E709 Task Switch Trace O VS1 Assist E709 VSTEH Vector STore Element (16) VRX D E70A I/O Interrupt Trace O VS1 Assist E70A VSTEG Vector STore Element (64) VRX D E70B Store ECPS:VS2 Level O VS1 Assist E70B VSTEF Vector STore Element (32) VRX D E70C Set Direct Translate Limit O VS1 Assist E70E VST Vector STore VRX D E710 PCB EnQueue LIFO O VS1 Assist E712 VGEG Vector Gather Element (64) VRV O E713 VGEF Vector Gather Element (32) VRV O E71A VSCEG Vector Scatter Element (64) VRV O E71B VSCEF Vector Scatter Element (32) VRV O E720 PCB EnQueue FIFO O VS1 Assist E721 VLGV Vector Load GR from VR Element VRS-c D E722 VLVG Vector Load VR Element from GR VRS-b D E727 LCBB Load Count to Block Boundary RXE O E730 Double Threaded Dequeue O VS1 Assist E730 VESL Vector Element Shift Left VRS-a S E733 VERLL Vector Element Rotate Left Logical VRS-a S E736 VLM Vector Load Multiple VRS-a D E737 VLL Vector Load with Length VRS-b D E738 VESRL Vector Element Shift Right Logical VRS-a S E73A VESRA Vector Element Shift Right Arithmetic VRS-a S E73E VSTM Vector STore Multiple VRS-a D E73F VSTL Vector STore with Length VRS-b D E740 Get APCBE O VS1 Assist E740 VLEIB Vector Load Element Immediate (8) VRI-a D E741 VLEIH Vector Load Element Immediate (16) VRI-a D E742 VLEIG Vector Load Element Immediate (64) VRI-a D E743 VLEIF Vector Load Element Immediate (32) VRI-a D E744 VGBM Vector Generate Byte Mask VRI-a O E745 VREPI Vector REPlicate Immediate VRI-a D E746 VGM Vector Generate Mask VRI-b O E74A VFTCI Vector FP Test data Class Immediate VRI-e L E74D VREP Vector REPlicate VRI-c D E750 Return APCBE O VS1 Assist E750 VPOPCT Vector POPulation CounT VRR-a O E752 VCTZ Vector CounT Trailing Zeros VRR-a A E753 VCLZ Vector CounT Leading Zeros VRR-a A E756 VLR Vector Load VRR-a D E758 Find Gotten Queue Element O VS1 Assist E75C VISTR Vector ISolate STRing VRR-a O E75F VSEG Vector Sign Extend to Doubleword VRR-a A E760 Dequeue Top APCBE O VS1 Assist E760 VMRL Vector MeRge Low VRR-c O E761 VMRH Vector MeRge High VRR-c O E762 VLVGP Vector Load VR from GRS disjoint VRR-f D E764 VSUM Vector SUM across word VRR-c A E765 VSUMG Vector SUM across Doubleword VRR-c A E766 VCKSM Vector ChecKSuM VRR-c A E767 VSUMQ Vector SUM across Quadword VRR-c A E768 SMF Storage Monitor O VS1 Assist E768 VN Vector aNd VRR-c A E769 VNC Vector aNd with Complement VRR-c A E76A VO Vector Or VRR-c A E76B VNO Vector NOr VRR-c A E76C VNX Vector Not eXclusive OR VRR-c A E76D VX Vector eXclusive OR VRR-c A E76E VNN Vector NaNd VRR-c A E76F VOC Vector OR with Complement VRR-c A E770 Enqueue RSPTE O VS1 Assist E770 VESLV Vector Element Shift Left VRR-c S E772 VERIM Vector Element Rotate and Insert under Mask VRI-d S E773 VERLLV Vector Element Rotate Left Logical VRR-c S E774 VSL Vector Shift Left VRR-c S E775 VSLB Vector Shift Left by Byte VRR-c S E777 VSLDB Vector Shift Left DOUBLE by Byte VRI-d S E778 GETMAIN PPA O VS1 Assist E778 VESRLV Vector Element Shift Right Logical VRR-c S E77A VESRAV Vector Element Shift Right Arithmetic VRR-c S E77C VSRL Vector Shift Right Logical VRR-c S E77D VSRLB Vector Shift Right Logical by Byte VRR-c S E77E VSRA Vector Shift Right Arithmetic VRR-c S E77F VSRAB Vector Shift Right Arithmetic by Byte VRR-c S E780 Enqueue RSPTE to Bottom O VS1 Assist E780 VFEE Vector Find Element Equal VRR-b O E781 VFENE Vector Find Element Not Equal VRR-b O E782 VFAE Vector Find Any Element Equal VRR-b O E784 VPDI Vector Permute Doubleword Immediate VRR-c O E785 VBPERM Vector BIT PERMute VRR-c S E786 VSLD Vector Shift Left Double by bit VRI-d S E787 VSRD Vector Shift Right Double by bit VRI-d S E788 GETMAIN PPA on Page Boundary O VS1 Assist E78A VSTRC Vector String Range Compare VRR-d L E78B VSTRS Vector String Search VRR-d O E78C VPERM Vector PERMute VRR-e S E78D VSEL Vector SELect VRR-e O E78E VFMS Vector FP Multiply and Subtract VRR-e A E78F VFMA Vector FP Multiply and Add VRR-e A E790 Dequeue Specific RSPTE O VS1 Assist E794 VPK Vector PacK VRR-c A E795 VPKLS Vector PacK Logical Saturate VRR-b A E797 VPKS Vector PacK Saturate VRR-b A E798 FREEMAIN PQA O VS1 Assist E79E VFNMS Vector FP Negative Multiply and Subtract VRR-e A E79F VFNMA Vector FP Negative Multiply and Add VRR-e A E7A0 Dequeue First RSPTE O VS1 Assist E7A1 VMLH Vector Multiply Logical High VRR-c A E7A2 VML Vector Multiply Low VRR-c A E7A3 VMH Vector Multiply High VRR-c A E7A4 VMLE Vector Multiply Logical Even VRR-c A E7A5 VMLO Vector Multiply Logical Odd VRR-c A E7A6 VME Vector Multiply EVen VRR-c A E7A7 VMO Vector Multiply Odd VRR-c A E7A8 FREEMAIN in Partition O VS1 Assist E7A9 VMALH Vector Multiply AND Add Logical High VRR-d A E7AA VMAL Vector Multiply AND Add Low VRR-d A E7AB VMAH Vector Multiply AND Add High VRR-d A E7AC VMALE Vector Multiply AND Add Logical Even VRR-d A E7AD VMALO Vector Multiply AND Add Logical Odd VRR-d A E7AE VMAE Vector Multiply AND Add Even VRR-d A E7AF VMAO Vector Multiply AND Add Odd VRR-d A E7B0 Invalidate Virtual Page O VS1 Assist E7B4 VGFM Vector Galois Field Multiply sum VRR-c A E7B8 Save GETMAIN/FREEMAIN Status O VS1 Assist E7B8 VMSL Vector Multiply Sum Logical VRR-d A E7B9 VACCC Vector Add with Carry Compute Carry VRR-d A E7BB VAC Vector Add with Carry VRR-d A E7BC VGFMA Vector Galois Field Multiply sum and Accumulate VRR-d A E7BD VSBCBI Vector Subtract with Borrow Compute Borrow Indication VRR-d A E7BF VSBI Vector Subtract with Borrow Indication VRR-d A E7C0 Short Term Unfix O VS1 Assist E7C0 VCLFP Vector FP Convert to Logical VRR-a D E7C0 VCLGD Vector FP Convert to Logical 64-bit VRR-a D E7C1 VCFPL Vector FP Convert from Logical VRR-a D E7C1 VCDLG Vector FP Convert from Logical 64-bit VRR-a D E7C2 VCSFP Vector FP Convert to Fixed VRR-a D E7C2 VCGD Vector FP Convert to Fixed 64-bit VRR-a D E7C3 VCFPS Vector FP Convert from Fixed VRR-a D E7C3 VCDG Vector FP Convert from Fixed 64-bit VRR-a D E7C4 VFLL Vector FP Load Lengthened VRR-a D E7C5 VFLR Vector FP Load Rounded VRR-a D E7C7 VFI Vector Load FP Integer VRR-a D E7C8 Restore GETMAIN/FREEMAIN Status O VS1 Assist E7CA WFK Vector FP Compare and Signal Scalar VRR-a L E7CB WFC Vector FP Compare Scalar VRR-a L E7CC VFPSO Vector FP Perform Sign Operation VRR-a A E7CE VFSQ Vector FP SQuare root VRR-a A E7D4 VUPLL Vector UnPack Logical Low VRR-a A E7D5 VUPLH Vector UnPack Logical High VRR-a A E7D6 VUPL Vector UnPack Low VRR-a A E7D7 VUPH Vector UnPack High VRR-a A E7D8 GETMAIN PQA O VS1 Assist E7D8 VTM Vector Test under Mask VRR-a L E7D9 VECL Vector Element Compare Logical VRR-a L E7DB VEC Vector Element Compare VRR-a L E7DE VLC Vector Load Complement VRR-a D E7DF VLP Vector Load Positive VRR-a D E7E0 Page Measurement O VS1 Assist E7E2 VFS Vector FP Subtract VRR-c A E7E3 VFA Vector FP Add VRR-c A E7E5 VFD Vector FP Divide VRR-c A E7E7 VFM Vector FP Multiply VRR-c A E7E8 Resume Group1 Suboperation O VS1 Assist E7E8 VFCE Vector FP Compare Equal VRR-c L E7EA VFCHE Vector FP Compare High or Equal VRR-c L E7EB VFCH Vector FP Compare High VRR-c L E7EE VFMIN Vector FP Minimum VRR-c L E7EF VFMAX Vector FP Maximum VRR-c L E7F0 Short Term Fix O VS1 Assist E7F0 VAVGL Vector AVeraGe Logical VRR-c A E7F1 VACC Vector Add Compute Carry VRR-c A E7F2 VAVG Vector AVeraGe VRR-c A E7F3 VA Vector Add VRR-c A E7F5 VSCBI Vector Subtract Compute Borrow Indication VRR-c A E7F7 VS Vector Subtract VRR-c A E7F8 Resume Group2 Suboperation O VS1 Assist E7F8 VCEQ Vector Compare EQual VRR-b L E7F9 VCHL Vector Compare High Logical VRR-b L E7FB VCH Vector Compare High VRR-b L E7FC VMNL Vector Minimum Logical VRR-c L E7FD VMXL Vector Maximum Logical VRR-c L E7FE VMN Vector Minimum VRR-c L E7FF VMX Vector Maximum VRR-c L E8 MVCIN MoVe Characters Inverse SS D E9 PKA Pack Ascii SS D EA UNPKA UnPacK Ascii SS D EA00 DIL SS O EA01 BDIL SS O EA04 ANUM SS O EA05 COMP SS O EA08 MCPU SS O EA09 MIO SS O EA0C BIFLAG SS O EA0D MULDIV SS O EB04 LMG Load Multiple Grande RSY-a D EB0A SRAG Shift Right single Arith. Grande RSY-a S EB0B SLAG Shift Left single Arith. Grande RSY-a S EB0C SRLG Shift Right single Log. Grande RSY-a S EB0D SLLG Shift Left single Log. Grande RSY-a S EB0F TRACG TRACe Grande RSY-a P EB14 CSY Compare and Swap (32) RSY-a L EB1C RLLG Rotate Left single Log. Grande RSY-a S EB1D RLL Rotate Left single Logical (32) RSY-a S EB20 CLMH Comp. Log. chars under Mask High RSY-b L EB21 CLMY Comp. Log. chars under Mask Yonder RSY-b L EB23 CLT Comp. Log. and Trap RSY-b L EB23-2 CLTH Comp. Log. and Trap on High RSY-b L EB23-4 CLTL Comp. Log. and Trap on Low RSY-b L EB23-7 CLTNE Comp. Log. and Trap on Not Equal RSY-b L EB23-8 CLTE Comp. Log. and Trap on Equal RSY-b L EB23-B CLTNL Comp. Log. and Trap on Not Low RSY-b L EB23-D CLTNH Comp. Log. and Trap on Not High RSY-b L EB24 STMG Store Multiple Grande RSY-a D EB25 STCTG STore ConTrol (64) RSY-a P EB26 STMH STore Multiple High RSY-a D EB2B CLT Comp. Log. and Trap (64) RSY-b L EB2C STCMH STore Characters under Mask (High) RSY-b D EB2D STCMY STore Characters under Mask (Low) RSY-b D EB2F LCTLG Load Control (64) RSY-a P EB30 CSG Compare and Swap (64) RSY-a L EB31 CDSY Compare Double and Swap (32) RSY-a L EB3E CDSG Compare Double and Swap (64) RSY-a L EB44 BXHG Branch on indeX High (64) RSY-a B EB45 BXLEG Branch on indeX Low or Equal (64) RSY-a B EB4C ECAG Extract CPU Attribute (Extr. Cache Attribute) RSY-a O EB51 TMY Test under Mask SIY L EB52 MVIY MoVe Immediate SIY D EB54 NIY aNd Immediate SIY D EB55 CLIY Compare Logical Immediate SIY L EB56 OIY Or Immediate SIY D EB57 XIY eXclusive or Immediate SIY D EB6A ASI Add Immediate (8/32) SIY A EB6E ALSI Add Logical with Signed Immediate (8/32) SIY A EB71 LPSWEY Load PSW Extended SIY P EB7A AGSI Add Immediate (8/64) SIY A EB7E ALGSI Add Logical with Signed Immediate (8/64) SIY A EB80 ICMH Insert Characters under Mask High RSY-b D EB81 ICMY Insert Characters under Mask RSY-b D EB8E MVCLU MoVe Character Long (Unicode) RSY-a D EB8F CLCLU Compare Logical Character Long (Unicode) RSY-a L EB96 LMH Load Multiple High RSY-a D EB98 LMY Load Multiple Yonder RSY-a D EB9A LAMY Load Access Multiple RSY-a D EBC0 TP Test Packed Decimal RSL-a L EBDC SRAK Shift Right sing. Arith. Keeping Source data RSY-a D EBDD SLAK Shift Left sing. Arith. Keeping Source data RSY-a D EBDE SRLK Shift Right sing. Logical Keeping Source data RSY-a D EBDF SRLK Shift Left sing. Logical Keeping Source data RSY-a D EBE0 LOCFH Load High on Condition (32) RSY-b O EBE1 STOCFH STore High on Condition RSY-b O EBE2 LOCG LOad on Condition Grande RSY-b D EBE3 STOCG STore on Condition (64) RSY-b D EBE4 LANG Load and aNd (64) RSY-a A EBE6 LAOG Load and OR (64) RSY-a A EBE7 LAXG Load and eXclusive or (64) RSY-a A EBE8 LAAG Load and Add (64) RSY-a A EBEA LAALG Load and Add Logical (64) RSY-a A EBF2 LOC Load on Condition (32) RSY-b D EBF3 STOC STore on Condition (32) RSY-b D EBF4 LAN Load and aNd (32) RSY-a A EBF6 LAO Load and OR (32) RSY-a A EBF7 LAX Load and eXclusive or (32) RSY-a A EBF8 LAA Load and Add (32) RSY-a A EBFA LAAL Load and Add Logical (32) RSY-a A EC42 LOCHI Load Halfword Immediate on Condition (32<16) RIE-g D EC44 BRXHG Branch Relative on indeX High RIE-e B EC45 BRXLG Branch Relative on indeX Low RIE-e B EC46 LOCGHI Load Halfword Immediate on Condition (64<16) RIE-g D EC4E LOCHHI Load Halfword High Immediate on Condition (32<16) RIE-g D EC51 RISBLG Rotate then Insert Selected Bits Low (64) RIE-f S EC54 RNSBG Rotate then aNd Selected Bits RIE-f S EC55 RISBG Rotate then Insert Selected Bits RIE-f S EC56 ROSBG Rotate then Or Selected Bits RIE-f S EC57 RXSBG Rotate then eXclusive OR Selected Bits RIE-f S EC59 RISBGN Rotate then Insert Selected Bits (64) RIE-f O EC5D RISBHG Rotate then Insert Selected Bits High (64) RIE-f O EC64 CGRJ Compare and Branch Relative (64) RIE-b L EC64-2 CGRJH Compare and Branch Relative on High (64) RIE-b L EC64-4 CGRJL Compare and Branch Relative on Low (64) RIE-b L EC64-7 CGRJNE Compare and Branch Relative on Not Equal (64) RIE-b L EC64-8 CGRJE Compare and Branch Relative on Equal (64) RIE-b L EC64-A CGRJNL Compare and Branch Relative on Not Low (64) RIE-b L EC64-C CGRJNH Compare and Branch Relative on Not High (64) RIE-b L EC65 CLGRJ Compare Logical and Branch Relative (64) RIE-b L EC65-2 CLGRJH Compare Logical and Branch Relative on High (64) RIE-b L EC65-4 CLGRJL Compare Logical and Branch Relative on Low (64) RIE-b L EC65-7 CLGRJNE Compare Logical and Branch Relative on Not Equal (64) RIE-b L EC65-8 CLGRJE Compare Logical and Branch Relative on Equal (64) RIE-b L EC65-A CLGRJNL Compare Logical and Branch Relative on Not Low (64) RIE-b L EC65-C CLGRJNH Compare Logical and Branch Relative on Not High (64) RIE-b L EC70 CGIT Compare Immediate and Trap (16/64) RIE-a L EC70-2 CGITH Compare Immediate and Trap on High (16/64) RIE-a L EC70-4 CGITL Compare Immediate and Trap on Low (16/64) RIE-a L EC70-7 CGITNE Compare Immediate and Trap on Not Equal (16/64) RIE-a L EC70-8 CGITE Compare Immediate and Trap on Equal (16/64) RIE-a L EC70-A CGITNL Compare Immediate and Trap on Not Low (16/64) RIE-a L EC70-C CGITNH Compare Immediate and Trap on Not High (16/64) RIE-a L EC71 CLGIT Compare Logical Immediate and Trap (16/64) RIE-a L EC71-2 CLGITH Compare Logical Immediate and Trap on High (16/64) RIE-a L EC71-4 CLGITL Compare Logical Immediate and Trap on Low (16/64) RIE-a L EC71-7 CLGITNE Compare Logical Immediate and Trap on Not Equal (16/64) RIE-a L EC71-8 CLGITE Compare Logical Immediate and Trap on Equal (16/64) RIE-a L EC71-A CLGITNL Compare Logical Immediate and Trap on Not Low (16/64) RIE-a L EC71-C CLGITNH Compare Logical Immediate and Trap on Not High (16/64) RIE-a L EC72 CIT Compare Immediate and Trap (16/32) RIE-a L EC72-2 CITH Compare Immediate and Trap on High (16/32) RIE-a L EC72-4 CITL Compare Immediate and Trap on Low (16/32) RIE-a L EC72-7 CITNE Compare Immediate and Trap on Not Equal (16/32) RIE-a L EC72-8 CITE Compare Immediate and Trap on Equal (16/32) RIE-a L EC72-A CITNL Compare Immediate and Trap on Not Low (16/32) RIE-a L EC72-C CITNH Compare Immediate and Trap on Not High (16/32) RIE-a L EC73 CLFIT Compare Logical Immediate and Trap (16/32) RIE-a L EC73-2 CLFITH Compare Logical Immediate and Trap on High (16/32) RIE-a L EC73-4 CLFITL Compare Logical Immediate and Trap on Low (16/32) RIE-a L EC73-7 CLFITNE Compare Logical Immediate and Trap on Not Equal (16/32) RIE-a L EC73-8 CLFITE Compare Logical Immediate and Trap on Equal (16/32) RIE-a L EC73-A CLFITNL Compare Logical Immediate and Trap on Not Low (16/32) RIE-a L EC73-C CLFITNH Compare Logical Immediate and Trap on Not High (16/32) RIE-a L EC76 CRJ Compare and Branch Relative (32) RIE-b L EC76-2 CRJH Compare and Branch Relative on High (32) RIE-b L EC76-4 CRJL Compare and Branch Relative on Low (32) RIE-b L EC76-7 CRJNE Compare and Branch Relative on Not Equal (32) RIE-b L EC76-8 CRJE Compare and Branch Relative on Equal (32) RIE-b L EC76-A CRJNL Compare and Branch Relative on Not Low (32) RIE-b L EC76-C CRJNH Compare and Branch Relative on Not High (32) RIE-b L EC77 CLRJ Compare Logical and Branch Relative (32) RIE-b L EC77-2 CLRJH Compare Logical and Branch Relative on High (32) RIE-b L EC77-4 CLRJL Compare Logical and Branch Relative on Low (32) RIE-b L EC77-7 CLRJNE Compare Logical and Branch Relative on Not Equal (32) RIE-b L EC77-8 CLRJE Compare Logical and Branch Relative on Equal (32) RIE-b L EC77-A CLRJNL Compare Logical and Branch Relative on Not Low (32) RIE-b L EC77-C CLRJNH Compare Logical and Branch Relative on Not High (32) RIE-b L EC7C CGIJ Compare Immediate and Branch Relative (8/64) RIE-c L EC7C-2 CGIJH Compare Immediate and Branch Relative (a High) RIE-c L EC7C-4 CGIJL Compare Immediate and Branch Relative (a Low) RIE-c L EC7C-7 CGIJNE Compare Immediate and Branch Relative Not Equal RIE-c L EC7C-8 CGIJE Compare Immediate and Branch Relative (a Equal b) RIE-c L EC7C-A CGIJNL Compare Immediate and Branch Relative (a Not Low) RIE-c L EC7C-C CGIJNH Compare Immediate and Branch Relative Not High RIE-c L EC7D CLGIJ Compare Log.Immed. and Branch Relative (8/64) RIE-c L EC7D-2 CLGIJH Compare Log.Immed. and Branch Relative (a High) RIE-c L EC7D-4 CLGIJL Compare Log.Immed. and Branch Relative (a Low) RIE-c L EC7D-7 CLGIJNE Compare Log.Immed. and Branch Relative Not Equal RIE-c L EC7D-8 CLGIJE Compare Log.Immed. and Branch Relative (a Equal b) RIE-c L EC7D-A CLGIJNL Compare Log.Immed. and Branch Relative (a Not Low) RIE-c L EC7D-C CLGIJNH Compare Log.Immed. and Branch Relative Not High RIE-c L EC7E CIJ Compare Immediate and Branch Relative (8/32) RIE-c L EC7E-2 CIJH Compare Immediate and Branch Relative (a High) RIE-c L EC7E-4 CIJL Compare Immediate and Branch Relative (a Low) RIE-c L EC7E-7 CIJNE Compare Immediate and Branch Relative Not Equal RIE-c L EC7E-8 CIJE Compare Immediate and Branch Relative (a Equal b) RIE-c L EC7E-A CIJNL Compare Immediate and Branch Relative (a Not Low) RIE-c L EC7E-C CIJNH Compare Immediate and Branch Relative Not High RIE-c L EC7F CLIJ Compare Log.Immed. and Branch Relative (8/32) RIE-c L EC7F-2 CLIJH Compare Log.Immed. and Branch Relative (a High) RIE-c L EC7F-4 CLIJL Compare Log.Immed. and Branch Relative (a Low) RIE-c L EC7F-7 CLIJNE Compare Log.Immed. and Branch Relative Not Equal RIE-c L EC7F-8 CLIJE Compare Log.Immed. and Branch Relative (a Equal b) RIE-c L EC7F-A CLIJNL Compare Log.Immed. and Branch Relative (a Not Low) RIE-c L EC7F-C CLIJNH Compare Log.Immed. and Branch Relative Not High RIE-c L ECD8 AHIK Add Immediate (32<16) RIE-d O ECD9 AGHIK Add Immediate (64<16) RIE-d O ECDA ALHSIK Add Logical with Signed Immediate (32<16) RIE-d O ECDB ALGHSIK Add Logical with Signed Immediate (64<16) RIE-d O ECE4 CGRB Compare and Branch (64) RRS L ECE4-2 CGRBH Compare and Branch on High (64) RRS L ECE4-4 CGRBL Compare and Branch on Low (64) RRS L ECE4-7 CGRBNE Compare and Branch on Not Equal (64) RRS L ECE4-8 CGRBE Compare and Branch on Equal (64) RRS L ECE4-A CGRBNL Compare and Branch on Not Low (64) RRS L ECE4-C CGRBNH Compare and Branch on Not High (64) RRS L ECE5 CLGRB Compare Logical and Branch (64) RRS L ECE5-2 CLGRBH Compare Logical and Branch on High (64) RRS L ECE5-4 CLGRBL Compare Logical and Branch on Low (64) RRS L ECE5-7 CLGRBNE Compare Logical and Branch on Not Equal (64) RRS L ECE5-8 CLGRBE Compare Logical and Branch on Equal (64) RRS L ECE5-A CLGRBNL Compare Logical and Branch on Not Low (64) RRS L ECE5-C CLGRBNH Compare Logical and Branch on Not High (64) RRS L ECF6 CRB Compare and Branch (32) RRS L ECF6-2 CRBH Compare and Branch (32) on High RRS L ECF6-4 CRBL Compare and Branch (32) on Low RRS L ECF6-7 CRBNE Compare and Branch (32) on Not Equal RRS L ECF6-8 CRBE Compare and Branch (32) on Equal RRS L ECF6-A CRBNL Compare and Branch (32) on Not Low RRS L ECF6-E CRBNH Compare and Branch (32) on Not High RRS L ECF7 CLRB Compare Logical and Branch (32) RRS L ECF7-2 CLRBH Compare Logical and Branch (32) on High RRS L ECF7-4 CLRBL Compare Logical and Branch (32) on Low RRS L ECF7-7 CLRBNE Compare Logical and Branch (32) on Not Equal RRS L ECF7-8 CLRBE Compare Logical and Branch (32) on Equal RRS L ECF7-A CLRBNL Compare Logical and Branch (32) on Not Low RRS L ECF7-C CLRBNH Compare Logical and Branch (32) on Not High RRS L ECFC CGIB Compare Immediate and Branch (8/64) RIS L ECFC-2 CGIBH Compare Immediate and Branch (a High) RIS L ECFC-4 CGIBL Compare Immediate and Branch (a Low) RIS L ECFC-7 CGIBNE Compare Immediate and Branch Not Equal RIS L ECFC-8 CGIBE Compare Immediate and Branch (a Equal b) RIS L ECFC-A CGIBNL Compare Immediate and Branch (a Not Low) RIS L ECFC-C CGIBNH Compare Immediate and Branch Not High RIS L ECFE CIB Compare Immediate and Branch (8/32) RIS L ECFE-2 CIBH Compare Immediate and Branch (a High) RIS L ECFE-4 CIBL Compare Immediate and Branch (a Low) RIS L ECFE-7 CIBNE Compare Immediate and Branch Not Equal RIS L ECFE-8 CIBE Compare Immediate and Branch (a Equal b) RIS L ECFE-A CIBNL Compare Immediate and Branch (a Not Low) RIS L ECFE-C CIBNH Compare Immediate and Branch Not High RIS L ED04 LDEB Load Lengthened (Short/Long) RXE D ED05 LXDB Load Lengthened (Long/Extended) RXE D ED06 LXEB Load Lengthened (Short/Extended) RXE D ED07 MXDB Multiply (Long/Extended) RXE A ED08 KEB Compare and Sign (Short) RXE L ED09 CEB Compare (Short) RXE L ED0A AEB Add (Short) RXE A ED0B SEB Subtract (Short) RXE A ED0C MDEB Multiply (Short) RXE A ED0D DEB Divide (Short) RXE A ED0E MAEB Multiply and Add (Short) RXF A ED0F MSEB Multiply and Subtract (Short) RXF A ED10 TCEB Test Data Class (Short) RXE L ED11 TCDB Test Data Class (Long) RXE L ED12 TCXB Test Data Class (Extended) RXE L ED14 SQEB Square Root (Short BFP) RXE A ED15 SQDB Square Root (Long BFP) RXE A ED17 MEEB Multiply RXE A ED18 KDB Compare and Sign (Long) RXE L ED19 CDB Compare (Long) RXE L ED1A ADB Add (Long) RXE A ED1B SDB Subtract (Long) RXE A ED1C MDB Multiply (Long) RXE A ED1D DDB Divide (Long) RXE A ED1E MADB Multiply and Add (Long) RXF A ED1F MSDB Multiply and Subtract (Long) RXF A ED24 LDE Load Lengthened (Short/Long) RXE A ED25 LXD Load Lengthened (Long/Extended) RXE A ED26 LXE Load Lengthened (Short/Extended) RXE A ED2E MAE Multiply and Add (Short) RXF A ED2F MSE Multiply and Subtract (Short) RXF A ED34 SQE Square Root (Short) RXE A ED35 SQD Square Root (Long) RXE A ED37 MEE Multiply (Short*Short to Short) RXE A ED38 MAYL Multiply and Add Unnormalized (Long>Ext. Low) RXF A ED39 MYL Multiply Unnormalized (Long>Ext. Low) RXF A ED3A MAY Multiply and Add Unnormalized (Long>Extended) RXF A ED3B MY Multiply Unnormalized (Long>Extended) RXF A ED3C MAYH Multiply and Add Unnormalized (Long>Ext. High) RXF A ED3D MYH Multiply Unnormalized (Long>Ext. High) RXF A ED3E MAD Multiply and Add (Long) RXF A ED3F MSD Multiply and Subtract (Long) RXF A ED40 SLDT Shift Significand Left (Long) RXF S ED41 SRDT Shift Significand Right (Long) RXF S ED48 SLXT Shift Significand Left (Extended) RXF S ED49 SRXT Shift Significand Right (Extended) RXF S ED50 TDCET Test Data Class (short DFP) RXE O ED51 TDGET Test Data Group (short DFP) RXE O ED54 TDCDT Test Data Class (long DFP) RXE O ED55 TDGDT Test Data Group (long DFP) RXE O ED58 TDCXT Test Data Class (extended DFP) RXE O ED59 TDGXT Test Data Group (extended DFP) RXE O ED64 LEY Load RXY-a D ED65 LDY Load Double RXY-a D ED66 STEY Store RXY-a D ED67 STDY Store Double RXY-a D EDA8 CZDT Convert to Zoned (Long/Zoned) RSL-b O EDA9 CZXT Convert to Zoned (Extended/Zoned) RSL-b O EDAA CDZT Convert from Zoned (Zoned/Long) RSL-b O EDAB CXZT Convert from Zoned (Zoned/Extended) RSL-b O EDAC CPDT Convert to PACKED (from long DFP) RSL-b O EDAD CPXT Convert to PACKED (from extended DFP) RSL-b O EDAE CDPT Convert from PACKED (to long DFP) RSL-b O EDAF CXPT Convert from PACKED (to extended DFP) RSL-b O EE PLO Perform Locked Operation SS-e D EF LMD Load Multiple Disjoint SS-e D F0 SRP Shift and Round Packed SS-c S F1 MVO Move with Offset SS-b D F2 PACK PACK SS-b A F3 UNPK UNPacK SS-b A F8 ZAP Zero and Add Packed SS-b A F9 CP Compare Packed SS-b L FA AP Add Packed SS-b A FB SP Subtract Packed SS-b A FC MP Multiply Packed SS-b A FD DP Divide Packed SS-b A LBEAR O LFI O LLGFI O LPSWEY O NNPA O QPACI O RDP O SLLHH O SLLHL O SLLLH O SRLHH O SRLHL O SRLLH O STBEAR O VCFN O VCLFNH O VCLFNL O VCLZDP O VCNF O VCRNF O VCSPH O VPKZR O VSCHDP O VSCHP O VSCHSP O VSCHXP O VSCSHP O VSRPR O VUPKZH O VUPKZL O [1] Technically, the DIAGNOSE instruction does not have a mnemonic, and is usually hard-coded in source. References z/Architecture Principles of Operations, IBM, SA22-7832-12, Thirteenth Edition (September, 2019) z/System Instructions, Operation Code Tables, Tachyon Software, http://www.tachyonsoft.com/inst390t.htm (Retrieved March 19, 2016) System/390 Instructions, Vector Instructions, Tachyon Software, http://www.tachyonsoft.com/inst390v.htm (Retrieved March 21, 2016) HLASM - List of All Opcodes, A. F. Kornelis, Bixsoft, http://www.bixoft.nl/english/opl_bobm.htm 2011 (Retrieved March 21, 2016) Assembler Language Programming for IBM System z™ Servers, Version 2.00, John R. Ehrman, IBM Silicon Valley Lab High Level Assembler support for IBM z16 instructions - APAR PH39324, https://www.ibm.com/support/pages/node/6567011