Electronics/Basic gates

Basic Gates There are 5 basic gates used in performing logic operations in Digital Electronic namely BUFFER gate, NOT gate, AND gate, OR gate, XOR gate . Each Logic Gate has A Symbol for easy to identify , a Mathematical Expression to identify mathematic logic operation and a Truth Table to completely describe operation of the Logic Gate Five Basic Logic Gates {| class="wikitable" width=100% ! Digital gates !! Symbol!! Logic Operation !! Mathematic Expression |- |BUFFER|| 100px|Cổng Tiếp (Buffer Gate) || Y = BUFFER A || Y = A |- |NOT || 100px || Y = NOT A || Y = |- |AND || 100px || Y = A AND B || Y = A . B |- |OR || 100px || Y = A OR B || Y = A + B |- |XOR || 100px || Y = A XOR B || Y = |- |} The Truth Table of the five basic logic gates above {| class="wikitable" width=100% ! A !! B !! Q = A !! Q = NOT A !! Q = A AND B !! Q = A OR B !! Q = A XOR B |- | 0 || 0 || 0 ||1 || 0 || 0 || 0 |- | 0 || 1 || 0 || 1 || 0 ||1 || 1 |- | 1 || 0 || 1 || 0 || 0 ||1 || 1 |- | 1 || 1 || 1 || 0 || 1 ||1 || 0 |- |} Complement of Basic Logic gates {| class="wikitable" width=100% !Basic Gates !! Combination Gates!! Symbol !! Mathematical Expression |- | BUFFER|| 100px 100px|Cổng NOT (NOT Gate) || 100px || Q = is NOT NOT A Y = A |- | NOT || 100px 100px|Cổng NOT (NOT Gate) || 100px|Cổng NOT (NOT Gate) || Y = is NOT A |- | NAND || 100px 100px|Cổng NOT (NOT Gate) || 100px || Q = NOT A AND B |- | NOR || 100px 100px|Cổng NOT (NOT Gate) || 100px || Y = NOT A OR B |- | XNOR || 100px 100px || 100px || Q = NOT A XOR B |- |} The Truth table of the combination gates above {| class="wikitable" width=100% ! A !! B !! Q = A !! Q = NOT A !! Q = A NAND B !! Q = A NOR B !! Q = A XNOR B |- | 0 || 0 || 0 ||1 || 1 || 1 || 1 |- | 0 || 1 || 0 || 1 || 1 || 0 || 0 |- | 1 || 0 || 1 || 0 || 1 || 0 || 0 |- | 1 || 1 || 1 || 0 || 0 || 0 || 1 |- |} Summary {| class=wikitable width=100% !rowspan=2|Gates !rowspan=2|Function !colspan=2|Symbol |- !ANSI!!IEC |- !Buffer | |File:Buffer ANSI Labelled.svg |File:Buffer IEC Labelled.svg |- !NOT gate (Inverter) | |File:NOT ANSI Labelled.svg |File:NOT IEC Labelled.svg |- !AND gate | |File:AND ANSI Labelled.svg |File:AND IEC Labelled.svg |- !NAND gate (NOT−AND) | |File:NAND ANSI Labelled.svg |File:NAND IEC Labelled.svg |- !OR gate | |File:OR ANSI Labelled.svg |File:OR IEC Labelled.svg |- !NOR gate (NOT−OR) | |File:NOR ANSI Labelled.svg |File:NOR IEC Labelled.svg |- !XOR gate (Exclusive-OR) | |File:XOR ANSI Labelled.svg |File:XOR IEC Labelled.svg |- !XNOR gate (NOT−exclusive−OR) | |File:XNOR ANSI Labelled.svg |File:XNOR IEC Labelled.svg |} {| class="wikitable" style="text-align:center; margin:auto;" ! width=3%| A !! width=3% | B !! width= 9% | Q = A !! width= 9% | Q = NOT A !! width= 9% | Q = A AND B !! width= 9% | Q = A OR B !! width= 9% | Q = A XOR B !! width= 9% | Q = A NAND B !! width= 9% | Q = A NOR B !! width= 9% | Q = A XNOR B |- | 0 || 0 || 0 ||1 || 0 || 0 || 0 || 1 ||1 || 1 |- | 0 || 1 || 0 || 1 || 0 ||1 || 1 || 1 ||0 || 0 |- | 1 || 0 || 1 || 0 || 0 ||1 || 1 || 1 ||0 || 0 |- | 1 || 1 || 1 || 0 || 1 ||1 || 0 || 0 ||0 || 1 |- |}