360 Assembly/360 Instructions/DR

__TOC__ DR - Divide by Register - Opcode 1D Format DR 2,7 The specific syntax is DR target register, source register. RR Instruction (2 bytes)Byte 1Byte 2target registersource register(8 bits)Opcode1D(4 bits) 0..F(4 bits)0..F The first argument is a one with lesser number of pair of target registers which value is affected by the instruction. The second argument is the source value register. Availability The DR instruction is available on all models of the 360, 370 and z/System. Operation The DR instruction divides the dividend - 64-bit signed value stored in pair of registers T and T+1, where T is target register number (T shall contain most significant part and T+1 shall contain least significant part), by the divisor - 32-bit signed value in the source register. The target register number T shall be even. The instruction places quotient to register T and remainder to register T+1, both as 32-bit signed values. The divisor shall not be zero. The quotient shall fit into limits of 32-bit signed value (-2147483648 till 2147483647). The DR instruction performs so-called T-division when quotient is truncated to zero; the remainder sign is equal to the dividend sign, if both values are not equal to 0; in other words, (remainder * dividend >= 0). The Condition Code field in the Program Status Word is not changed. Exceptions and Faults If an odd register number is specified as the target register, operation exception occurs. If the divisor is zero, operation exception occurs. If signed integer overflow is detected and the bit 36 in PSW is set, operation exception occurs. Example Consider that register 4 contains 0, 5 - 13 and 11 - 4. The instruction "DR 4,11" will divide the contents of register 13 by 4, place the quotient (equals to 3) in register 4 and place the remainder (equals to 1) in register 5. Related instructions To divide by word value from memory, see D. To multiply by word value from register, see MR. To subtract word value from register, see SR. To add value and set condition codes according to unsigned arithmetic, or add not most significant part of multi-word integer value, see AL or ALR. To divide floating-point values, see DER, DDR, DE or DD. DP DSG 1C MR 1E ALR