10 nm process

MOSFET technology node March 2022 In semiconductor fabrication, the International Technology Roadmap for Semiconductors (ITRS) defines the "10 nanometer process" as the MOSFET technology node following the "14 nm" node. Since at least 1997, "process nodes" have been named purely on a marketing basis, and have no relation to the dimensions on the integrated circuit;https://www.eejournal.com/article/no-more-nanometers/ No More Nanometers – EEJournal 23 July 2020 neither gate length, metal pitch or gate pitch on a "10nm" device is ten nanometers.https://www.design-reuse.com/articles/43316/a-brief-history-of-process-node-evolution.html A Brief History of Process Node Evolution Shukla Priyank design-reuse.com 2019-07-09https://www.extremetech.com/computing/184946-14nm-7nm-5nm-how-low-can-cmos-go-it-depends-if-you-ask-the-engineers-or-the-economists 14nm, 7nm, 5nm: How low can CMOS go? It depends if you ask the engineers or the economists... Hruska Joel ExtremeTechhttps://wccftech.com/intel-losing-process-lead-analysis-7nm-2022/ Exclusive: Is Intel Really Starting To Lose Its Process Lead? 7nm Node Slated For Release in 2022 wccftech.com 2016-09-10 For example, GlobalFoundries' "7 nm" processes are dimensionally similar to Intel's "10 nm" process.https://www.eejournal.com/article/life-at-10nm-or-is-it-7nm-and-3nm/ Life at 10nm. (Or is it 7nm?) And 3nm - Views on Advanced Silicon Platforms eejournal.com 2018-03-12 TSMC and Samsung's "10 nm" processes are somewhere between Intel's "14 nm" and "10 nm" processes in transistor density. The transistor density (number of transistors per square millimetre) is more important than transistor size, since smaller transistors no longer necessarily mean improved performance, or an increase in the number of transistors.June 2024 All production "10 nm" processes are based on FinFET (fin field-effect transistor) technology, a type of multi-gate MOSFET technology that is a non-planar evolution of planar silicon CMOS technology. Samsung first started their production of "10 nm-class" chips in 2013 for their multi-level cell (MLC) flash memory chips, followed by their SoCs using their 10 nm process in 2016. TSMC began commercial production of "10 nm" chips in 2016, and Intel later began production of "10nm" chips in 2018.February 2024 Background The ITRS's original naming of this technology node was "11 nm". According to the 2007 edition of the roadmap, by the year 2022, the half-pitch (i.e., half the distance between identical features in an array) for a DRAM was projected to be 11 nm. In 2008, Pat Gelsinger, at the time serving as Intel's Chief Technology Officer, said that Intel saw a 'clear way' towards the "10 nm" node.Intel's Gelsinger Sees Clear Path To 10nm Chips Damon Poeter http://www.crn.com/hardware/208801780 https://web.archive.org/web/20090425061704/http://www.crn.com/hardware/208801780 2009-04-25 live 2009-06-20 July 2008 MIT: Optical lithography good to 12 nanometers http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 https://web.archive.org/web/20120925204010/http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=209400807 2012-09-25 live 2009-06-20 In 2011, Samsung announced plans to introduce the "10nm" process the following year.World's Largest Fabrication Facility, Line-16 https://news.samsung.com/global/world%E2%80%99s-largest-memory-fabrication-facility-line-16memory 21 June 2019 Samsung September 26, 2011February 2024 In 2012, Samsung announced eMMC flash memory chips that are produced using the "10nm" process.Samsung's new 10nm-process 64GB mobile flash memory chips are smaller, faster, better https://www.engadget.com/2012/11/15/samsung-10nm-64gb-emmc-mobile-flash-memory/ 21 June 2019 Engadget November 15, 2012 As of 2018, "10 nm" as it was generally understood was only in high-volume production at Samsung. GlobalFoundries had skipped "10 nm",February 2024 Intel had not yet started high-volume "10 nm" production, due to yield issues,February 2024 and TSMC had considered "10 nm" to be a short-lived node,http://techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/ 10nm rollout 2018-08-04 2018-08-04 https://web.archive.org/web/20180804110423/http://techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/ dead mainly dedicated to processors for Apple during 2017–2018, moving on to "7 nm" in 2018.February 2024 There is also a distinction to be made between "10 nm" as marketed by foundries and "10 nm" as marketed by DRAM companies. Technology production history In April 2013, Samsung announced that it had begun mass production of multi-level cell (MLC) flash memory chips using a "10nm-class" process, which, according to Tom's Hardware, Samsung defined as "a process technology node somewhere between 10-nm and 20-nm".Samsung Mass Producing 128Gb 3-bit MLC NAND Flash https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html 21 June 2019 Tom's Hardware 11 April 2013 21 June 2019 https://web.archive.org/web/20190621175628/https://www.tomshardware.co.uk/NAND-128Gb-Mass-Production-3-bit-MLC,news-43458.html dead On 17 October 2016, Samsung Electronics announced mass production of SoC chips at "10 nm". https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology Oct 2016 The technology's main announced challenge at that time had been triple patterning for its metal layer.https://news.samsung.com/global/samsung-starts-industrys-first-mass-production-of-system-on-chip-with-10-nanometer-finfet-technology Samsung Starts Industry's First Mass Production of System-on-Chip with 10-Nanometer FinFET Technology news.samsung.comhttp://www.cse.cuhk.edu.hk/~byu/papers/N01-SPIE-TPL.pdf triple patterning for 10nm metalFebruary 2024 TSMC began commercial production of "10 nm" chips in early 2016, before moving onto mass production in early 2017.10nm Technology https://www.tsmc.com/english/dedicatedFoundry/technology/10nm.htm TSMC 30 June 2019 On 21 April 2017, Samsung started shipping their Galaxy S8 smartphone, which used the company's version of the "10 nm" processor.http://www.samsung.com/us/explore/galaxy-s8/buy/ BuyFebruary 2024 On 12 June 2017, Apple delivered second-generation iPad Pro tablets powered with TSMC-produced Apple A10X chips using the "10 nm" FinFET process.http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/ 10nm Rollout Marching Right Along techinsights.com techinsights.com 2017-06-30 https://web.archive.org/web/20170803141307/http://www.techinsights.com/about-techinsights/overview/blog/10nm-rollout-marching-right-along/ 2017-08-03 dead On 12 September 2017, Apple announced the Apple A11, a 64-bit ARM-based system on a chip, manufactured by TSMC using a "10 nm" FinFET process, containing 4.3 billion transistors on a die of 87.66 mm2. In April 2018, Intel announced a delay in volume production of "10 nm" mainstream CPUs until sometime in 2019.https://www.fool.com/investing/2018/04/29/intel-corp-delays-10nm-chip-production.aspx Intel Corp. Delays 10nm Chip Production - Mass production is now scheduled for 2019. 2018-04-29 2018-08-01 In July, the exact time was further pinned down to the holiday season.https://arstechnica.com/gadgets/2018/07/intel-says-not-to-expect-mainstream-10nm-chips-until-2h19/ Intel says not to expect mainstream 10nm chips until 2H19 2018-07-28 2018-08-01 In the meantime, however, they did release a low-power "10 nm" mobile chip, albeit exclusive to Chinese markets and with much of the chip disabled.https://www.tomshardware.com/news/intel-10nm-processor-core-i3-8121u,37054.html Intel's First 10nm Processor Lands In China 2018-05-15 2018-09-11 Tom's HardwareFebruary 2024 In June 2018 at VLSI 2018, Samsung announced their "11LPP" and "8LPP" processes. "11LPP" was a hybrid based on Samsung "14 nm" and "10 nm" technology. "11LPP" was based on their "10 nm" BEOL, not their "20 nm" BEOL like the "14LPP". "8LPP" was based on the "10LPP" process.https://fuse.wikichip.org/news/1425/vlsi-2018-samsungs-11nm-11lpp/ VLSI 2018: Samsung's 11nm nodelet, 11LPP 2018-06-30 WikiChip Fuse en-US 2019-05-31 11 May 2024 https://web.archive.org/web/20240511164941/https://fuse.wikichip.org/news/1425/vlsi-2018-samsungs-11nm-11lpp/ deadhttps://fuse.wikichip.org/news/1443/vlsi-2018-samsungs-8nm-8lpp-a-10nm-extension/ VLSI 2018: Samsung's 8nm 8LPP, a 10nm extension 2018-07-01 WikiChip Fuse en-US 2019-05-31 11 May 2024 https://web.archive.org/web/20240511164932/https://fuse.wikichip.org/news/1443/vlsi-2018-samsungs-8nm-8lpp-a-10nm-extension/ deadFebruary 2024 Nvidia released their GeForce 30 series GPUs in September 2020. They were at that time made on a custom version of Samsung's "8 nm" process, called "Samsung 8N", with a transistor density of 44.56 million transistors per mm2.https://www.pcgamer.com/amp/nvidia-ampere-samsung-8nm-process/ Nvidia confirms Samsung 8nm process for RTX 3090, RTX 3080, and RTX 3070 PC Gamer www.pcgamer.com September 2020 James Dave https://wccftech.com/nvidia-geforce-rtx-30-series-ampere-graphics-cards-deep-dive/ NVIDIA GeForce RTX 30 Ampere GPU Deep-Dive, Full Specs, Thermals, Power & Performance Detailed September 4, 2020February 2024 Process nodes Foundry ITRS Logic DeviceGround Rules (2015) Samsung TSMC Intel Processname 16/14 nm 11/10 nm 10LPE(10 nm) 10LPP(10 nm) 8LPP(8 nm) 8LPU(8 nm) 8LPA(8 nm) 8N 10FF(10 nm) 10nmhttps://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros https://archive.today/20210726212343/https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros dead 26 July 2021 Intel's Process Roadmap to 2025: With 4nm, 3nm, 20A and 18A?! 10nm+ 10nm SF(10 nm++)For 10nm ESF renamed Intel 7, see 7 nmIntel 7 September 2023 Transistor density (MTr/mm2) 51.82 61.18 55.7552.51https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/ TSMC Announces 6-Nanometer Process Schor David 2019-04-16 WikiChip Fuse en-US 2019-05-31 15 November 2022 https://web.archive.org/web/20221115172838/https://fuse.wikichip.org/news/2261/tsmc-announces-6-nanometer-process/ dead 60.41https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/2/ A Look At Intel 4 Process Technology Schor David 2022-06-19 WikiChip Fuse 20 April 2025 24 March 2025 https://web.archive.org/web/20250324084253/https://fuse.wikichip.org/news/6720/a-look-at-intel-4-process-technology/2/ dead (100.76)https://hexus.net/tech/news/cpu/119699-intel-10nm-density-27x-improved-14nm-node/ Intel 10nm density is 2.7X improved over its 14nm node HEXUS 2018-11-14 en-GBIntel uses this formula:https://newsroom.intel.com/editorials/lets-clear-up-node-naming-mess/ Let's Clear Up the Node Naming Mess Bohr Mark 2017-03-28 Intel Newsroom 2018-12-06 Transistorgate pitch (nm) 70 48 68 64 64/68 66 54 Interconnect pitch (nm) 56 36 51 colspan="2" 44 36 Transistor fin pitch (nm) 42 36 42 42 36 34 Transistor fin height (nm) 42 42 49 44 48 42 53 Production year 2015 2017 2016 Q4 productionhttps://www.anandtech.com/show/10765/samsung-10nm-massproduction https://web.archive.org/web/20161018121659/http://www.anandtech.com/show/10765/samsung-10nm-massproduction dead 18 October 2016 Samsung Foundry Announces 10nm SoC In Mass-Production Andrei Frumusanu www.anandtech.com 2017 Q4 productionhttps://www.anandtech.com/show/12096/samsung-starts-10lpp-mass-production https://web.archive.org/web/20171129195702/https://www.anandtech.com/show/12096/samsung-starts-10lpp-mass-production dead 29 November 2017 Samsung Starts Mass Production of Chips Using 10nm Low Power Plus (10LPP) Process Tech Anton Shilov www.anandtech.com 2018 production 2018 risk production2019 productionhttps://www.anandtech.com/show/13329/samsung-foundry-updates-8lpu-for-2019 https://web.archive.org/web/20180906221137/https://www.anandtech.com/show/13329/samsung-foundry-updates-8lpu-for-2019 dead 6 September 2018 Samsung Foundry Updates: 8LPU Added, EUVL on Track for HVM in 2019 Anton Shilov www.anandtech.com 2021 production 2020 production 2016 risk production2017 production 2018 productionhttps://www.semiaccurate.com/2018/08/02/intel-guts-10nm-to-get-it-out-the-door/ Intel guts 10nm to get it out the door Demerjian Charlie 2018-08-02 SemiAccurate 6 September 2024 (Cannon Lake)Cutress Ian July 26, 2021 Intel's Process Roadmap to 2025: with 4nm, 3nm, 20A and 18A?! https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros https://archive.today/20210726212343/https://www.anandtech.com/show/16823/intel-accelerated-offensive-process-roadmap-updates-to-10nm-7nm-4nm-3nm-20a-18a-packaging-foundry-emib-foveros dead 26 July 2021 AnandTech 2021-07-27 2019 production (Ice Lake) 2020 production (Tiger Lake)https://www.anandtech.com/show/16107/what-products-use-intel-10nm-superfin-demystified/3 https://web.archive.org/web/20200929105416/https://www.anandtech.com/show/16107/what-products-use-intel-10nm-superfin-demystified/3 dead 29 September 2020 What Products Use Intel 10nm? SuperFin and 10++ Demystified Transistor gate pitch is also referred to as CPP (contacted poly pitch) and interconnect pitch is also referred to as MMP (minimum metal pitch). Samsung reported their "10 nm" process as having a 64 nm transistor gate pitch and 48 nm interconnect pitch. TSMC reported their "10 nm" process as having a 64 nm transistor gate pitch and 42 nm interconnect pitch. Further investigation by Tech Insights revealed even these values to be false, and they have been updated accordingly. In addition, the transistor fin height of Samsung's "10 nm" process was updated by MSSCORPS CO at SEMICON Taiwan 2017.http://hothardware.com/news/intel-details-advanced-10nm-node Intel Details Cannonlake's Advanced 10nm FinFET Node, Claims Full Generation Lead Over Rivals 2017-03-28 2017-03-30 2017-03-30 https://web.archive.org/web/20170330151945/http://hothardware.com/news/intel-details-advanced-10nm-node deadhttps://www.semiconductors.org/wp-content/uploads/2018/06/0_2015-ITRS-2.0-Executive-Report-1.pdf International Technology Roadmap for Semiconductors 2.0 2015 Edition Executive Report 2018-12-27https://semiwiki.com/semiconductor-manufacturers/intel/6713-14nm-16nm-10nm-and-7nm-what-we-know-now/ 14nm 16nm 10nm and 7nm - What we know now Scotten Jones 25 February 2024 http://www.techinsights.com/about-techinsights/overview/blog/qualcomm-snapdragon-835-first-to-10-nm/ Qualcomm Snapdragon 835 First to 10 nm Samsung 10LPE process https://en.wikichip.org/wiki/10_nm_lithography_process 10 nm lithography process wikichip 22 July 2017 1 July 2019 https://web.archive.org/web/20190701083338/https://en.wikichip.org/wiki/10_nm_lithography_process dead GlobalFoundries decided not to develop a "10 nm" node, because it believed it would be short lived.https://semiwiki.com/semiconductor-manufacturers/globalfoundries/6879-exclusive-globalfoundries-discloses-7nm-process-detail/ Exclusive - GLOBALFOUNDRIES discloses 7nm process detail Scotten Jones 25 February 2024 Samsung's "8 nm" process was at that time the company's last to exclusively use DUV lithography.https://www.anandtech.com/show/11946/samsungs-8lpp-process-technology-qualified-ready-for-production https://web.archive.org/web/20171019184126/https://www.anandtech.com/show/11946/samsungs-8lpp-process-technology-qualified-ready-for-production dead 19 October 2017 Samsung's 8LPP Process Technology Qualified, Ready for Production Anton Shilov www.anandtech.comFebruary 2024 DRAM "10 nm class" Dynamic random-access memory For the DRAM industry, the term "10 nm-class" is often used and this dimension generally refers to the half-pitch of the active area.April 2019 The "10 nm" foundry structures are generally much larger.April 2019 Generally "10 nm class" refers to DRAM with a 10-19 nm feature size, and was first introduced around 2016. As of 2020, there were three generations of "10 nm class" DRAM : 1x nm (19-17 nm, Gen1); 1y nm (16-14 nm, Gen2); and 1z nm (13-11 nm, Gen3).https://blocksandfiles.com/2020/04/13/dram-is-stuck-in-a-10nm-process-trap/ Why DRAM is stuck in a 10nm trap Chris Mellor 13 April 2020 blocksandfiles.com 3rd Generation "1z" DRAM was first introduced 2019 by Samsung, and was initially stated to be produced using ArF lithography without the use of EUV lithography; https://www.anandtech.com/show/14118/samsung-develops-8-gb-drams-using-3rd-gen-10nmclass-process-technology https://web.archive.org/web/20190322122724/https://www.anandtech.com/show/14118/samsung-develops-8-gb-drams-using-3rd-gen-10nmclass-process-technology dead 22 March 2019 Samsung Develops Smaller DDR4 Dies Using 3rd Gen 10nm-Class Process Tech Anton Shilov 21 March 2019 www.anandtech.com https://news.samsung.com/my/samsung-develops-industrys-first-3rd-generation-10nm-class-dram-for-premium-memory-applications Samsung Develops Industry's First 3rd-generation 10nm-Class DRAM for Premium Memory Applications 25 Mar 2019 Samsung press release subsequent production did utilise EUV lithography. https://news.samsung.com/my/samsung-announces-industrys-first-euv-dram-with-shipment-of-first-million-modules Samsung Announces Industry's First EUV DRAM with Shipment of First Million Modules 25 Mar 2020 Samsung press release Beyond 1z Samsung named its next node (fourth generation "10 nm class") DRAM : "D1a" (expected at that time to have been produced in 2021), and beyond that "D1b" (expected at that time to have been produced in 2022)February 2024; whilst Micron referredFebruary 2024 to succeeding "nodes" as "D1α" and "D1β".https://www.eetimes.com/teardown-samsungs-d1z-dram-with-euv-lithography/ www.eetimes.com Jeongdong Choe 18 Feb 2021 Teardown: Samsung's D1z DRAM with EUV Lithography Micron announced volume shipment of 1α class DRAM in early 2021.https://investors.micron.com/news-releases/news-release-details/micron-delivers-industrys-first-1a-dram-technology Micron Delivers Industry's First 1α DRAM Technology 26 Jan 2021 Micron press release References 30em 14 nm 7 nm MOSFET manufacturing processes *00010