128-bit computing

Computer architecture bit width December 2019 March 2026 128 (16 octets) October 2026, there are no mainstream general-purpose processors built to operate on 128-bit integers or addresses, although a number of processors do have specialized ways to operate on 128-bit chunks of data as summarized in Hardware. Representation A processor with 128-bit byte addressing could directly address up to 2128 (over 3.40 38) bytes, which would greatly exceed the total data captured, created, or replicated on Earth as of 2024, which has been estimated to be around 149 zettabytes (over 276 bytes).Reinsel David Gantz John Rydning John The Digitalization of the World from Edge to Core https://www.seagate.com/files/www-content/our-story/trends/files/idc-seagate-dataage-whitepaper.pdf Seagate Technology IDC 14 September 2021 https://web.archive.org/web/20210907102915/https://www.seagate.com/files/www-content/our-story/trends/files/idc-seagate-dataage-whitepaper.pdf 7 September 2021 3 en November 2018 liveBig data statistics: How much data is there in the world? https://rivery.io/blog/big-data-statistics-how-much-data-is-there-in-the-world/ A 128-bit register can store 2128 (over 3.40 × 1038) different values. The range of integer values that can be stored in 128 bits depends on the integer representation used. With the two most common representations, the range is 0 through 340, 282, 366, 920, 938, 463, 463, 374, 607, 431, 768, 211, 455 (2128 − 1) for representation as an (unsigned) binary number, and −170, 141, 183, 460, 469, 231, 731, 687, 303, 715, 884, 105, 728 (−2127) through 170, 141, 183, 460, 469, 231, 731, 687, 303, 715, 884, 105, 727 (2127 − 1) for representation as two's complement. Quadruple precision (128 bits) floating-point numbers can store 113-bit fixed-point numbers or integers accurately without losing precision (thus 64-bit integers in particular). Quadruple precision floats can also represent any position in the observable universe with at least micrometer precision.May 2020 Decimal128 floating-point numbers can represent numbers with up to 34 significant digits. Hardware A 128-bit multicomparator was described by researchers in 1976.Mead Carver A. Carver Mead Pashley Richard D. Britton Lee D. Daimon Yoshiaki T. Sando Stewart F. Jr. October 1976 128-Bit Multicomparator https://authors.library.caltech.edu/53685/1/01050799.pdf live IEEE Journal of Solid-State Circuits 11 5 692–695 10.1109/JSSC.1976.1050799 1976IJSSC..11..692M 27262034 https://web.archive.org/web/20181103205511/https://authors.library.caltech.edu/53685/1/01050799.pdf 3 November 2018 The IBM System/360 Model 85,10.1147/sj.71.0022 7 Structural aspects of the System/360 Model 85, III: Extensions to floating-point architecture 1968 IBM Systems Journal 22–29 Padegs A and IBM System/370 and its successors, support 128-bit floating-point arithmetic. The Siemens 7.700 and 7.500 series mainframes and their successors support 128-bit floating-point arithmetic.Assembler Instructions (BS2000/OSD) U3119-J-Z125-2-7600 1993 https://bs2manuals.ts.fujitsu.com/download/manual/959.1 Most modern CPUs feature single instruction, multiple data (SIMD) instruction sets (Streaming SIMD Extensions, AltiVec etc.) where 128-bit vector registers are used to store several smaller numbers, such as four 32-bit floating-point numbers. A single instruction can then operate on all these values in parallel. However, these processors do not operate on individual numbers that are 128 binary digits in length; only their vector registers have the size of 128 bits. The DEC VAX supported operations on 128-bit integer ('O' or octaword) and 128-bit floating-point ('H-float' or HFLOAT) datatypes. Support for such operations was an upgrade option rather than being a standard feature. Since the VAX's registers were 32 bits wide, a 128-bit operation used four consecutive registers or four longwords in memory. The ICL 2900 Series provided a 128-bit accumulator, and its instruction set included 128-bit floating-point and packed decimal arithmetic. A CPU with 128-bit multimedia extensions was designed by researchers in 1999.Suzuoki M. Kutaragi K. Hiroi T. Magoshi H. Okamoto S. Oka M. Ohba A. Yamamoto Y. Furuhashi M. November 1999 A microprocessor with a 128-bit CPU, ten floating-point MAC's, four floating-point dividers, and an MPEG-2 decoder IEEE Journal of Solid-State Circuits 34 11 1608–1618 10.1109/4.799870 Tanaka M. Yutaka T. Okada T. Nagamatsu M. Urakawa Y. Funyu M. Kunimatsu A. Goto H. Hashimoto K. Ide N. Murakami H. Ohtaguro Y. Aono A. 1999IJSSC..34.1608S Among the sixth generation of video game consoles, the Dreamcast and the PlayStation 2 used the term 128-bit in their marketing to describe their capability. The PlayStation 2's CPU had 128-bit SIMD capabilities.John L. Hennessy John L. Hennessy David A. Patterson David Patterson (scientist) Computer Architecture: A Quantitative Approach 2003 Morgan Kaufmann Publishers Third 1-55860-724-2Keith Diefendorff Keith Diefendorff Sony's Emotionally Charged Chip Microprocessor Report 13 5 April 19, 1999 Microdesign Resources Neither console supported 128-bit addressing or 128-bit integer arithmetic. The RISC-V ISA specification from 2016 includes a reservation for a 128-bit version of the architecture, but the details remain undefined intentionally, because there is yet so little practical experience with such large word size.Waterman Andrew Asanović Krste Krste Asanović The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA version 2.2 EECS-2016-118 https://riscv.org/technical/specifications/ University of California, Berkeley 25 May 2017 Software In the same way that compilers emulate, e.g., 64-bit integer arithmetic on architectures with register sizes less than 64 bits, some compilers also support 128-bit integer arithmetic. For example, the GCC C compiler 4.6 and later has a 128-bit integer type __int128 for some architectures.GCC 4.6 Release Series – Changes, New Features, and Fixes https://gcc.gnu.org/gcc-4.6/changes.html 25 July 2016 GCC and compatible compilers signal the presence of 128-bit arithmetic when the macro __SIZEOF_INT128__ is defined. 128-bit integer – nonsensical documentation? Marc Glisse August 26, 2015 GCC-Help https://gcc.gnu.org/ml/gcc-help/2015-08/msg00185.html January 23, 2020 For the C programming language, 128-bit support is optional, e.g. via the int128_t type, or it can be implemented by a compiler-specific extension. The Rust programming language has built-in support for 128-bit integers (originally via LLVM), which is implemented on all platforms.i128 – Rust https://doc.rust-lang.org/std/primitive.i128.html 2020-06-25 doc.rust-lang.org A 128-bit type provided by a C compiler can be available in Perl via the Math::Int128 module.Math::Int128 https://metacpan.org/pod/Math::Int128 metacpan.org 2020-06-25 The C3 programming language provides an implementation of a 128-bit integer data type.Types https://c3-lang.org/language-overview/types/ 2026-06-12 C3 Programming Language en Other uses Universally unique identifiers (UUID) consist of a 128-bit value. IPv6 routes computer network traffic amongst a 128-bit range of addresses. ZFS is a 128-bit file system. 128 bits is a common key size for symmetric ciphers and a common block size for block ciphers in cryptography. The IBM i Machine Interface defines all pointers as 128-bit. The Machine Interface instructions are translated to the hardware's real instruction set as required, allowing the underlying hardware to change without needing to recompile the software. Past hardware had a CISC instruction set with 48-bit addressing, while current hardware is 64-bit PowerPC/Power ISA. In the PowerPC/Power ISA implementation, the first four bytes contain information used to identify the type of the object being referenced, and the final eight bytes are used as a virtual memory address.Inside the AS/400, Second Edition https://books.google.com/books?id=5DoPAAAACAAJ 978-1-882419-66-1 Frank G. Soltis 1997 Duke Press The remaining four bytes are unused, and would allow IBM i applications to be extended to 96-bit addressing in future without requiring code changes. Increasing the word size can speed up multiple precision mathematical libraries, with applications to cryptography, and potentially speed up algorithms used in complex mathematical processing (numerical analysis, signal processing, complex photo editing and audio and video processing). MD5 is a hash function producing a 128-bit hash value. Apache Avro uses a 128-bit random number as synchronization marker for efficient splitting of data files.https://mail-archives.apache.org/mod_mbox/avro-user/201301.mbox/%3CCAHNLEqvRrdA3qhGmDs8jCXGP-TeK24DTmZ1sfDgfu10mW=PB0Q@mail.gmail.com%3E Re: Synchronization Markers Kleppmann Martin 24 January 2013 https://web.archive.org/web/20150927205705/https://mail-archives.apache.org/mod_mbox/avro-user/201301.mbox/%3CCAHNLEqvRrdA3qhGmDs8jCXGP-TeK24DTmZ1sfDgfu10mW=PB0Q@mail.gmail.com%3E 27 September 2015 livehttps://avro.apache.org/docs/1.8.0/spec.html#Object+Container+Files Apache Avro 1.8.0 Specification Apache Software Foundation References Category:Data unit